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ADV7320KSTZ Folha de dados(PDF) 8 Page - Analog Devices |
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ADV7320KSTZ Folha de dados(HTML) 8 Page - Analog Devices |
8 / 88 page ADV7320/ADV7321 Rev. 0 | Page 8 of 88 TIMING SPECIFICATIONS VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V, VDD_IO = 2.375 V to 3.6 V, VREF = 1.235 V, RSET = 3040 Ω, RLOAD = 300 Ω. All specifications TMIN to TMAX (0°C to 70°C), unless otherwise noted. Table 4. Parameter Min Typ Max Unit Test Conditions MPU PORT1 SCLOCK Frequency 0 400 kHz SCLOCK High Pulse Width, t1 0.6 µs SCLOCK Low Pulse Width, t2 1.3 µs Hold Time (Start Condition), t3 0.6 µs First clock generated after this period relevant for repeated start condition Setup Time (Start Condition), t4 0.6 µs Data Setup Time, t5 100 ns SDATA, SCLOCK Rise Time, t6 300 ns SDATA, SCLOCK Fall Time, t7 300 ns Setup Time (Stop Condition), t8 0.6 µs RESET Low Time 100 ns ANALOG OUTPUTS Analog Output Delay2 7 ns Output Skew 1 ns CLOCK CONTROL AND PIXEL PORT3 fCLK 29.5 MHz SD PAL square pixel mode fCLK 81 MHz PS/HD async mode Clock High Time, t9 40 % of one clk cycle Clock Low Time, t10 40 % of one clk cycle Data Setup Time, t111 2.0 ns Data Hold Time, t121 2.0 ns SD Output Access Time, t13 15 ns SD Output Hold Time, t14 5.0 ns HD Output Access Time, t13 14 ns HD Output Hold Time, t14 5.0 ns PIPELINE DELAY4 63 clk cycles SD (2×, 16×) 76 clk cycles SD component mode (16×) 35 clk cycles PS (1×) 41 clk cycles PS (8×) 36 clk cycles HD (2×, 1×) 1 Guaranteed by characterization. 2 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition. 3 Data: C[9:0]; Y[9:0], S[9:0] Control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK 4 SD, PS = 27 MHz, HD = 74.25 MHz. |
Nº de peça semelhante - ADV7320KSTZ |
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Descrição semelhante - ADV7320KSTZ |
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