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74F776 Folha de dados(PDF) 2 Page - NXP Semiconductors |
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74F776 Folha de dados(HTML) 2 Page - NXP Semiconductors |
2 / 12 page Philips Semiconductors Product specification 74F776 Pi–bus transceiver 2 December 19, 1990 853 1121 01321 FEATURES • Octal latched transceiver • Drives heavily loaded backplanes with equivalent load impedances down to 10 ohms • High drive (100mA) open collector drivers on B port • Reduced voltage swing (1 volt) produces less noise and reduces power consumption • High speed operation enhances performance of backplane buses and facilitates incident wave switching • Compatible with Pi–bus and IEEE 896 Futurebus standards • Built–in precision band–gap reference provides accurate receiver thresholds and improved noise immunity • Controlled output ramp and multiple GND pins minimize ground bounce • Glitch–free power up/power down operation • Multiple package options • Industrial temperature range available (–40°C to +85°C) DESCRIPTION The 74F776 is an octal bidirectional latched transceiver and is intended to provide the electrical interface to a high performance wired–OR bus. The B port inverting drivers are low–capacitance open collector with controlled ramp and are designed to sink 100mA from 2 volts. The B port inverting receivers have a 100 mV threshold region and a 4ns glitch filter. The 74F776 B port interfaces to ’Backplane Transceiver Logic’ (BTL). BTL features a reduced (1V to 2V) voltage swing for lower power consumption and a series diode on the drivers to reduce capacitive loading. Incident wave switching is employed, therefore BTL propagation delays are short. Although the voltage swing is less for BTL, so is its receiver threshold, therefore noise margins are excellent. BTL offers low power consumption, low ground bounce, EMI and crosstalk, low capacitive loading, superior noise margin and low propagation delays. This results in a high bandwidth, reliable backplane. The 74F776 A port has TTL 3–state drivers and TTL receivers with a latch function. A separate high–level control voltage input (VX) is provided to limit the A side output level to a given voltage level (such as 3.3V). For 5.0V systems, VX is simply tied to VCC. The 74F776 has a designed feature to control the B output transitions during power sequencing. There are two possible sequencing, They are as follows: 1.When LE = low and OEBn = low then the B outputs are disabled until the LE circuitry takes control. Then the B outputs will follow the A inputs, making a maximum of one transition during power–up (or down). 2. If LE = high or OEBn = high then the B outputs will be disabled during power–up (or down). TYPE TYPICAL PROPAGA- TION DELAY TYPICAL SUPPLY CURRENT( TOTAL) 74F776 6.5ns 80mA ORDERING INFORMATION ORDER CODE COMMERCIAL RANGE INDUSTRIAL RANGE DESCRIPTION VCC = 5V ±10%, Tamb = 0°C to +70°C VCC = 5V ±10%, Tamb = –40°C to +85°C PKG DWG # 28–pin plastic DIP (600 mil) N74F776N I74F776N SOT117-2 28–pin PLCC N74F776A I74F776A SOT261-2 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS DESCRIPTION 74F (U.L.) HIGH/LOW LOAD VALUE HIGH/LOW A0 – A7 PNP latched inputs 3.5/0.117 70 µA/70µA B0 – B7 Data inputs with threshold circuitry 5.0/0.167 100 µA/100µA OEA A output enable input (active high) 1.0/0.033 20 µA/20µA OEB0, OEB1 B output enable inputs (active low) 1.0/0.033 20 µA/20µA LE Latch enable input (active low) 1.0/0.033 20 µA/20µA A0 – A7 3–state outputs 150/40 3mA/24mA B0 – B7 Open collector outputs OC/166.7 OC/100mA Notes to input and output loading and fan out table One (1.0) FAST unit load is defined as: 20 µA in the high state and 0.6mA in the low state. OC = Open collector. |
Nº de peça semelhante - 74F776 |
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Descrição semelhante - 74F776 |
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