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74HC112N Folha de dados(PDF) 2 Page - NXP Semiconductors

Nome de Peças 74HC112N
Descrição Electrónicos  Dual JK flip-flop with set and reset; negative-edge trigger
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Fabricante Electrônico  PHILIPS [NXP Semiconductors]
Página de início  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

74HC112N Folha de dados(HTML) 2 Page - NXP Semiconductors

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1998 Jun 10
2
Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
negative-edge trigger
74HC/HCT112
FEATURES
• Asynchronous set and reset
• Output capability: standard
• ICC category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT112 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT112 are dual negative-edge triggered
JK-type flip-flops featuring individual nJ, nK, clock (nCP),
set (nSD) and reset (nRD) inputs.
The set and reset inputs, when LOW, set or reset the
outputs as shown in the function table regardless of the
levels at the other inputs.
A HIGH level at the clock (nCP) input enables the nJ and
nK inputs and data will be accepted. The nJ and nK inputs
control the state changes of the flip-flops as shown in the
function table. The nJ and nK inputs must be stable one
set-up time prior to the HIGH-to-LOW clock transition for
predictable operation.
Output state changes are initiated by the HIGH-to-LOW
transition of nCP.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; Tamb =25 °C; tr =tf = 6 ns
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
HC
HCT
tPHL/ tPLH
propagation delay
CL = 15 pF; VCC =5 V
nCP to nQ, nQ
1719ns
nSD to nQ, nQ
1515ns
nRD to nQ, nQ
1819ns
fmax
maximum clock frequency
66
70
MHz
CI
input capacitance
3.5
3.5
pF
CPD
power dissipation capacitance per flip-flop
notes 1 and 2
27
30
pF


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