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STE2004DIE2 Folha de dados(PDF) 1 Page - STMicroelectronics |
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STE2004DIE2 Folha de dados(HTML) 1 Page - STMicroelectronics |
1 / 66 page 1/66 STE2004 July 2004 1 FEATURES ■ 102 x 65 bits Display Data RAM ■ Programmable MUX rate ■ Programmable Frame Rate ■ X,Y Programmable Carriage Return ■ Dual Partial Display Mode ■ Row by Row Scrolling ■ N-Line Inversion ■ Automatic data RAM Blanking procedure ■ Selectable Input Interface: • I2C Bus Fast and Hs-mode (read and write) • 68000 & 8080 Parallel Interfaces (read and write) • 3-lines and 4-lines SPI Interface (read and write) • 3-lines 9 bit Serial Interface (read and write) ■ Fully Integrated Oscillator requires no external components ■ CMOS Compatible Inputs ■ Fully Integrated Configurable LCD bias voltage generator with: • Selectable multiplication factor (up to 5X) • Effective sensing for High Precision Output • Eight selectable temperature compensation coefficients ■ Designed for chip-on-glass (COG) applications. ■ Low Power Consumption, suitable for battery operated systems ■ Logic Supply Voltage range from 1.7 to 3.6V ■ High Voltage Generator Supply Voltage range from 1.75 to 4.5V ■ Display Supply Voltage range from 4.5 to 14.5V ■ Backward Compatibility with STE2001/2 2 DESCRIPTION The STE2004 is a low power CMOS LCD control- ler driver. Designed to drive a 65 rows by 102 col- umns graphic display, it provides all necessary functions in a single chip, including on-chip LCD supply and bias voltages generators, resulting in a minimum of externals components and in a very low power consumption. STE2004 features six standard interfaces (3-lines Serial, 3-lines SPI, 4-lines SPI, 68000 Parallel, 8080 parallel & I2C) for ease of interfacing with the host micro-controller Table 1. Order Codes Part Numbers Type STE2004DIE1 Bumped Wafers STE2004DIE2 Bumped Dice on Waffle Pack 102 X 65 SINGLE CHIP LCD CONTROLLER / DRIVER Figure 1. Block Diagram COLUMN DRIVERS ROW DRIVERS DATA LATCHES 65 x 102 RAM DISPLAY CONTROL LOGIC SCROLL LOGIC DATA REGISTER INSTRUCTION REGISTER CO to C101 R0 to R64 VSENSE SLAVE RES VDD1,2 CLOCK TIMING GENERATOR BIAS VOLTAGE GENERATOR HIGH VOLTAGE GENERATOR RESET TEST SHIFT REGISTER VLCD VSS SEL1,2 EXT ICON_MODE VSSAUX SAO SDIN/SDA_IN SDA_OUT SCLK/SCL DB0 to DB7 9 Bit SERIAL D/C CS SA1 SDOUT E/WR R/W- RD I2C BUS 3 & 4 Line SPI Parallel 8080 Parallel 68K SEL 0 SEL 1 SEL 2 TEST_VREF TEST_MODE LR0047 OSC OSC_IN OSC_OUT FR_IN FR_OUT MASTER SLAVE SYNC VLCDSENSE Rev. 4 |
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