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M27C202-150N1TR Folha de dados(PDF) 8 Page - STMicroelectronics |
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M27C202-150N1TR Folha de dados(HTML) 8 Page - STMicroelectronics |
8 / 15 page M27C202 8/15 Figure 6. Programming and Verify Modes AC Waveforms tAVPL VALID AI00706 A0-A15 Q0-Q15 VPP VCC P G DATA IN DATA OUT E tQVPL tVPHPL tVCHPL tPHQX tPLPH tGLQV tQXGL tELPL tGHQZ tGHAX PROGRAM VERIFY Figure 7. Programming Flowchart AI00707C n= 0 Last Addr VERIFY P = 100 µs Pulse ++n =25 ++ Addr VCC = 6.25V, VPP = 12.75V FAIL CHECK ALL WORDS 1st: VCC =6V 2nd: VCC = 4.2V YES NO YES NO YES NO PRESTO II Programming Algorithm PRESTO II Programming Algorithm allows pro- gramming of the whole array with a guaranteed margin, in a typical time of 13 seconds. Program- ming with PRESTO II consists of applying a se- quence of 100 µs program pulses to each word until a correct verify occurs (see Figure 7). During programming and verify operation, a MARGIN MODE circuit is automatically activated in order to guarantee that each cell is programmed with enough margin. No overprogram pulse is applied since the verify in MARGIN MODE provides nec- essary margin to each programmed cell. Program Inhibit Programming of multiple M27C202s in parallel with different data is also easily accomplished. Ex- cept for E, all like inputs including G of the parallel M27C202 may be common. A TTL low level pulse applied to a M27C202’s P input, with E low and VPP at 12.75V, will program that M27C202. A high level E input inhibits the other M27C202s from be- ing programmed. Program Verify A verify (read) should be performed on the pro- grammed bits to determine that they were correct- ly programmed. The verify is accomplished with E and G at VIL, P at VIH,VPP at 12.75V and VCC at 6.25V. |
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