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74LVC841APW Folha de dados(PDF) 2 Page - NXP Semiconductors

Nome de Peças 74LVC841APW
Descrição Electrónicos  10-bit transparent latch with 5-volt tolerant inputs/outputs 3-State
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Fabricante Electrônico  PHILIPS [NXP Semiconductors]
Página de início  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

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Philips Semiconductors
Product specification
74LVC841A
10-bit transparent latch with 5-volt tolerant
inputs/outputs (3-State)
2
1998 Jun 17
853-2071 19589
FEATURES
5-volt tolerant inputs/outputs, for interfacing with 5-volt logic
Wide supply voltage range of 1.2 V to 3.6 V
In accordance with the JEDEC standard no. 8-1 A
Inputs accept voltages up to 5.5 V
CMOS low power consumption
Direct interface with TTL levels
Flow-through pin-out architecture
DESCRIPTION
The 74LVC841A is a low-power, low-voltage, Si-gate CMOS device
and superior to most advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. In 3-State
operation, outputs can handle 5 V. This feature allows the use of
these devices as translators in a mixed 3.3 V/5 V environment. The
74LVC841A is a 10-bit transparent latch featuring separate D-type
inputs for each latch and 3-State outputs for bus oriented
applications. A latch enable (LE) input and an output enable (OE)
input are common to all internal latches. The 74LVC841A consists of
ten transparent latches with 3-State true outputs. When LE is HIGH,
data at the Dn inputs enters the latches. In this condition the latches
are transparent, i.e., a latch output will change each time its
corresponding D-input changes. When LE is LOW the latches store
the information that was present at the D-inputs a set-up time
preceding the HIGH-to-LOW transition of LE. When OE is LOW, the
contents of the ten latches are available at the outputs.
When OE is HIGH, the outputs go to the high impedance OFF-state.
Operation of the OE input does not affect the state of the latches.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25°C; tr =tf ≤ 2.5 ns
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
tPHL/tPLH
Propagation delay
Dn to Qn;
LE to Qn
CL = 50 pF;
VCC = 3.3 V
4.5
5.0
ns
CI
Input capacitance
5.0
pF
CPD
Power dissipation capacitance per latch
VI = GND to VCC1
22
pF
NOTE:
1CPD is used to determine the dynamic power dissipation (PD in µW)
PD = CPD × VCC2 × fi ) (CL × VCC2 × fo) where:
fi = input frequency in MHz; CL = output load capacity in pF;
fo = output frequency in MHz; VCC = supply voltage in V;
(CL × VCC2 × fo) = sum of the outputs.
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE
OUTSIDE NORTH AMERICA
NORTH AMERICA
PKG. DWG. #
24-Pin Plastic SO
–40
°C to +125°C
74LVC841A D
74LVC841A D
SOT137-1
24-Pin Plastic SSOP Type II
–40
°C to +125°C
74LVC841A DB
74LVC841A DB
SOT340-1
24-Pin Plastic TSSOP Type I
–40
°C to +125°C
74LVC841A PW
7LVC841APW DH
SOT355-1
PIN CONFIGURATION
24
23
1
SV01723
D0
D1
D2
D3
D4
D5
D6
GND
D7
D8
D9
Q0
Q1
Q2
Q3
Q4
VCC
Q5
Q6
Q7
Q8
Q9
LE
2
3
4
5
6
7
8
9
10
11
12
20
21
22
19
18
17
16
15
14
13
OE
PIN DESCRIPTION
PIN NUMBER
SYMBOL
NAME AND FUNCTION
1
OE
Output enable input (active Low)
2, 3, 4, 5, 6, 7, 8,
9, 10, 11
D0 to D9
Data inputs
23, 22, 21, 20, 19,
18, 17, 16, 15, 14
Q0 to Q9
3-state latch outputs
12
GND
Ground (0 V)
13
LE
Latch enable input (active HIGH)
24
VCC
Positive supply voltage


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