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MC145480P Folha de dados(PDF) 9 Page - Motorola, Inc |
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MC145480P Folha de dados(HTML) 9 Page - Motorola, Inc |
9 / 24 page MC145480 MOTOROLA 9 PC BOARD MOUNTING It is recommended that the device be soldered to the PC board for optimum noise performance. If the device is to be used in a socket, it should be placed in a low parasitic pin inductance (generally, low–profile) socket. POWER SUPPLY, GROUND, AND NOISE CONSIDERATIONS This device is intended to be used in switching applica- tions which often require plugging the PC board into a rack with power applied. This is known as ‘‘hot–rack insertion.’’ In these applications care should be taken to limit the voltage on any pin from going positive of the VDD pins, or negative of the VSS pins. One method is to extend the ground and power contacts of the PCB connector. The device has input protec- tion on all pins and may source or sink a limited amount of current without damage. Current limiting may be accom- plished by series resistors between the signal pins and the connector contacts. The most important considerations for PCB layout deal with noise. This includes noise on the power supply, noise generated by the digital circuitry on the device, and cross coupling digital or radio frequency signals into the audio sig- nals of this device. The best way to prevent noise is to: 1. Keep digital signals as far away from audio signals as possible. 2. Keep radio frequency signals as far away from the audio signals as possible. 3. Use short, low inductance traces for the audio circuitry to reduce inductive, capacitive, and radio frequency noise sensitivities. 4. Use short, low inductance traces for digital and RF circuitry to reduce inductive, capacitive, and radio frequency radiated noise. 5. Bypass capacitors should be connected from the VDD and VAG pins to VSS with minimal trace length. Ceramic monolithic capacitors of about 0.1 µF are acceptable to decouple the device from its own noise. The VDD capacitor helps supply the instantaneous currents of the digital circuitry in addition to decoupling the noise which may be generated by other sections of the device or other circuitry on the power supply. The VAG decoupling capacitor helps to reduce the impedance of the VAG pin to VSS at frequencies above the bandwidth of the VAG generator, which reduces the susceptibility to RF noise. 6. Use a short, wide, low inductance trace to connect the VSS ground pin to the power supply ground. The VSS pin is the digital ground and the most negative power supply pin for the analog circuitry. All analog signal processing is referenced to the VAG pin, but because digital and RF circuitry will probably be powered by this same ground, care must be taken to minimize high frequency noise in the VSS trace. Depending on the application, a double– sided PCB with a VSS ground plane connecting all of the digital and analog VSS pins together would be a good grounding method. A multilayer PC board with a ground plane connecting all of the digital and analog VSS pins together would be the optimal ground configuration. These methods will result in the lowest resistance and the lowest inductance in the ground circuit. This is important to reduce voltage spikes in the ground circuit resulting from the high speed digital current spikes. The magnitude of digitally induced voltage spikes may be hundreds of times larger than the analog signal the device is required to digitize. 7. Use a short, wide, low inductance trace to connect the VDD power supply pin to the 5 V power supply. Depending on the application, a double–sided PCB with VDD bypass capacitors to the VSS ground plane, as described above, may complete the low impedance coupling for the power supply. For a multilayer PC board with a power plane, connecting all of the VDD pins to the power plane would be the optimal power distribution method. The integrated circuit layout and packaging considerations for the 5 V VDD power circuit are essentially the same as for the VSS ground circuit. 8. The VAG pin is the reference for all analog signal processing. In some applications the audio signal to be digitized may be referenced to the VSS ground. To reduce the susceptibility to noise at the input of the ADC section, the three–terminal op amp may be used in a differential to single–ended circuit to provide level conversion from the VSS ground to the VAG ground with noise cancellation. The op amp may be used for more than 35 dB of gain in microphone interface circuits, which will require a compact layout with minimum trace lengths as well as isolation from noise sources. It is recom- mended that the layout be as symmetrical as possible to avoid any imbalances which would reduce the noise cancelling benefits of this differential op amp circuit. Refer to the application schematics for examples of this circuitry. If possible, reference audio signals to the VAG pin instead of to the VSS pin. Handset receivers and tele- phone line interface circuits using transformers may be audio signal referenced completely to the VAG pin. Re- fer to the application schematics for examples of this circuitry. The VAG pin cannot be used for ESD or line protection. 9. For applications using multiple MC145480 PCM Codec– Filters, the VAG pins cannot be tied together. The VAG pins are capable of sourcing and sinking current and will each be driving the node, which will result in large contention currents, crosstalk susceptibilities, and in- creased noise. 10. The MC145480 is fabricated with advanced high–speed CMOS technology that is capable of responding to noise pulses on the clock pins of 1 ns or less. It should be noted that noise pulses of such short duration may not be seen with oscilloscopes that have less bandwidth than 600 MHz. The most often encountered sources of clock noise spikes are inductive or capacitive coupling of high–speed logic signals, and ground bounce. The best solution for addressing clock spikes from coupling is to separate the traces and use short low inductance PC board traces. To address ground bounce problems, all integrated circuits should have high frequency bypass capacitors directly across their power supply pins, with low inductance traces for ground and power supply. A less than optimum solution may be to limit the bandwidth of the trace by adding series resistance and/or capaci- tance at the input pin. |
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