5-1

FACT DATA

Dual DType Positive

EdgeTriggered FlipFlop

The MC74AC74/74ACT74 is a dual D-type flip-flop with Asynchronous Clear

and Set inputs and complementary (Q,Q) outputs. Information at the input is

transferred to the outputs on the positive edge of the clock pulse. Clock triggering

occurs at a voltage level of the clock pulse and is not directly related to the transition

time of the positive-going pulse. After the Clock Pulse input threshold voltage has

been passed, the Data input is locked out and information present will not be

transferred to the outputs until the next rising edge of the Clock Pulse input.

Asynchronous Inputs:

LOW input to SD (Set) sets Q to HIGH level

LOW input to CD (Clear) sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on CD and SD makes both Q and Q HIGH

• Outputs Source/Sink 24 mA

• ′ACT74 Has TTL Compatible Inputs

CP1

CD2

CP2

13

14

12

11

10

9

8

2

1

3

4

5

6

7

VCC

CD1

D1

CP1

SD1

Q1

Q1

CD2

D2

CP2

SD2

Q2

Q2

CD1

SD1

Q1

D1

SD2

Q2

Q2

D2

GND

Q1

PIN NAMES

D1, D2

Data Inputs

CP1, CP2

Clock Pulse Inputs

CD1, CD2

Direct Clear Inputs

SD1, SD2

Direct Set Inputs

Q1, Q1, Q2, Q2

Outputs

TRUTH TABLE (Each Half)

Inputs

Outputs

SD

CD

CP

D

Q

Q

L

H

X

X

H

L

H

L

X

X

L

H

L

L

X

X

H

H

H

H

H

H

L

H

H

L

L

H

H

H

L

X

Q0

Q0

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

= LOW-to-HIGH Clock Transition

Q0(Q0) = Previous Q(Q) before

LOW-to-HIGH Transition of Clock

MC74AC74

MC74ACT74

DUAL D-TYPE POSITIVE

EDGE-TRIGGERED

FLIP-FLOP

N SUFFIX

CASE 646-06

PLASTIC

D SUFFIX

CASE 751A-03

PLASTIC

LOGIC SYMBOL

SD1

Q1

CP1

Q1

CD1

SD2

Q2

D2

CP2

Q2

CD2

D1