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ADC0803CD Folha de dados(PDF) 6 Page - NXP Semiconductors |
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ADC0803CD Folha de dados(HTML) 6 Page - NXP Semiconductors |
6 / 18 page Philips Semiconductors Product data ADC0803/0804 CMOS 8-bit A/D converters 2002 Oct 17 6 Large values of source resistance where an input bypass capacitor is not used will not cause errors as the input currents settle out prior to the comparison time. If a low pass filter is required in the system, use a low valued series resistor (< 1 k Ω) for a passive RC section or add an op amp active filter (low pass). For applications with source resistances at or below 1 k Ω, a 0.1 µF bypass capacitor at the inputs will prevent pickup due to series lead inductance or a long wire. A 100 Ω series resistor can be used to isolate this capacitor (both the resistor and capacitor should be placed out of the feedback loop) from the output of the op amp, if used. Analog Differential Voltage Inputs and Common-Mode Rejection These A/D converters have additional flexibility due to the analog differential voltage input. The VIN(–) input (Pin 7) can be used to subtract a fixed voltage from the input reading (tare correction). This is also useful in a 4/20 mA current loop conversion. Common-mode noise can also be reduced by the use of the differential input. The time interval between sampling VIN(+) and VIN(–) is 4.5 clock periods. The maximum error due to this time difference is given by: V(max) = (VP) (2fCM) (4.5/fCLK), where: V = error voltage due to sampling delay VP = peak value of common-mode voltage fCM = common mode frequency For example, with a 60 Hz common-mode frequency, fcm, and a 1 MHz A/D clock, fCLK, keeping this error to 1/4 LSB (about 5 mV) would allow a common-mode voltage, VP, which is given by: V P + [V(max) (f CLK) (2f CM)(4.5) or V P + (5 x 10*3)(104) (6.28) (60) (4.5) + 2.95V The allowed range of analog input voltages usually places more severe restrictions on input common-mode voltage levels than this, however. An analog input span less than the full 5 V capability of the device, together with a relatively large zero offset, can be easily handled by use of the differential input. (See Reference Voltage Span Adjust). Noise and Stray Pickup The leads of the analog inputs (Pins 6 and 7) should be kept as short as possible to minimize input noise coupling and stray signal pick-up. Both EMI and undesired digital signal coupling to these inputs can cause system errors. The source resistance for these inputs should generally be below 5 k Ω to help avoid undesired noise pickup. Input bypass capacitors at the analog inputs can create errors as described previously. Full scale adjustment with any input bypass capacitors in place will eliminate these errors. Reference Voltage For application flexibility, these A/D converters have been designed to accommodate fixed reference voltages of 5V to Pin 20 or 2.5 V to Pin 9, or an adjusted reference voltage at Pin 9. The reference can be set by forcing it at VREF/2 input, or can be determined by the supply voltage (Pin 20). Figure 6 indicates how this is accomplished. Reference Voltage Span Adjust Note that the Pin 9 (VREF/2) voltage is either 1/2 the voltage applied to the VCC supply pin, or is equal to the voltage which is externally forced at the VREF/2 pin. In addition to allowing for flexible references and full span voltages, this also allows for a ratiometric voltage reference. The internal gain of the VREF/2 input is 2, making the full-scale differential input voltage twice the voltage at Pin 9. For example, a dynamic voltage range of the analog input voltage that extends from 0 to 4 V gives a span of 4 V (4–0), so the VREF/2 voltage can be made equal to 2 V (half of the 4 V span) and full scale output would correspond to 4 V at the input. On the other hand, if the dynamic input voltage had a range of 0.5 to 3.5 V, the span or dynamic input range is 3 V (3.5–0.5). To encode this 3 V span with 0.5 V yielding a code of zero, the minimum expected input (0.5 V, in this case) is applied to the VIN(–) pin to account for the offset, and the VREF/2 pin is set to 1/2 the 3 V span, or 1.5 V. The A/D converter will now encode the VIN(+) signal between 0.5 and 3.5 V with 0.5 V at the input corresponding to a code of zero and 3.5 V at the input producing a full scale output code. The full 8 bits of resolution are thus applied over this reduced input voltage range. The required connections are shown in Figure 7. Operating Mode These converters can be operated in two modes: 1) absolute mode 2) ratiometric mode In absolute mode applications, both the initial accuracy and the temperature stability of the reference voltage are important factors in the accuracy of the conversion. For VREF/2 voltages of 2.5 V, initial errors of ±10 mV will cause conversion errors of ±1 LSB due to the gain of 2 at the VREF/2 input. In reduced span applications, the initial value and stability of the VREF/2 input voltage become even more important as the same error is a larger percentage of the VREF/2 nominal value. See Figure 8. In ratiometric converter applications, the magnitude of the reference voltage is a factor in both the output of the source transducer and the output of the A/D converter, and, therefore, cancels out in the final digital code. See Figure 9. Generally, the reference voltage will require an initial adjustment. Errors due to an improper reference voltage value appear as full-scale errors in the A/D transfer function. ERRORS AND INPUT SPAN ADJUSTMENTS There are many sources of error in any data converter, some of which can be adjusted out. Inherent errors, such as relative accuracy, cannot be eliminated, but such errors as full-scale and zero scale offset errors can be eliminated quite easily. See Figure 7. Zero Scale Error Zero scale error of an A/D is the difference of potential between the ideal 1/2 LSB value (9.8 mV for VREF/2=2.500 V) and that input voltage which just causes an output transition from code 0000 0000 to a code of 0000 0001. If the minimum input value is not ground potential, a zero offset can be made. The converter can be made to output a digital code of 0000 0000 for the minimum expected input voltage by biasing the VIN(–) input to that minimum value expected at the VIN(–) input to that minimum value expected at the VIN(+) input. This uses the differential mode of the converter. Any offset adjustment should be done prior to full scale adjustment. |
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