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DESCRIPTION

SN74SSTUB32866

SCAS792 – OCTOBER 2006

25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST

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Supports SSTL_18 Data Inputs

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Member of the Texas Instruments

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Differential Clock (CLK and CLK) Inputs

Widebus+™ Family

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Supports LVCMOS Switching Levels on the

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Pinout Optimizes DDR2 DIMM PCB Layout

Control and RESET Inputs

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Configurable as 25-Bit 1:1 or 14-Bit 1:2

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Checks Parity on DIMM-Independent Data

Registered Buffer

Inputs

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Chip-Select Inputs Gate the Data Outputs

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Able to Cascade with a Second

from Changing State and Minimizes System

SN74SSTUB32866

Power Consumption

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RESET Input Disables Differential Input

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Output Edge-Control Circuitry Minimizes

Receivers, Resets All Registers, and Forces

Switching Noise in an Unterminated Line

All Outputs Low, Except QERR

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the

1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout

configuration, two devices per DIMM are required to drive 18 SDRAM loads.

All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are

edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except the

open-drain error (QERR) output.

The SN74SSTUB32866 operates from a differential clock (CLK and CLK). Data are registered at the crossing of

CLK going high and CLK going low.

The SN74SSTUB32866 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input,

compares it with the data received on the DIMM-independent D-inputs (D2–D3, D5–D6, D8–D25 when C0 = 0

and C1 = 0; D2–D3, D5–D6, D8–D14 when C0 = 0 and C1 = 1; or D1-D6, D8-D13 when C0 = 1 and C1 = 1)

and indicates whether a parity error has occurred on the open-drain QERR pin (active low). The convention is

even parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs,

combined with the parity input bit. To calculate parity, all DIMM-independent data inputs must be tied to a known

logic state.

When used as a single device, the C0 and C1 inputs are tied low. In this configuration, parity is checked on the

PAR_IN input signal, which arrives one cycle after the input data to which it applies. Two clock cycles after the

data are registered, the corresponding partial-parity-out (PPO) and QERR signals are generated.

When used in pairs, the C0 input of the first register is tied low, and the C0 input of the second register is tied

high. The C1 input of both registers are tied high. Parity, which arrives one cycle after the data input to which it

applies, is checked on the PAR_IN input signal of the first device. Two clock cycles after the data are registered,

the corresponding PPO and QERR signals are generated on the second device. The PPO output of the first

register is cascaded to the PAR_IN of the second SN74SSTUB32866. The QERR output of the first

SN74SSTUB32866 is left floating, and the valid error information is latched on the QERR output of the second

SN74SSTUB32866.

ORDERING INFORMATION

ORDERABLE PART NUMBER

TOP-SIDE MARKING

0

°C to 70°C

LFBGA–ZKE

Tape and reel

SN74SSTUB32866ZKER

SB866

(1)

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus+ is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Copyright © 2006, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.