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AD5533ABC-1 Folha de dados(PDF) 4 Page - Analog Devices |
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AD5533ABC-1 Folha de dados(HTML) 4 Page - Analog Devices |
4 / 16 page REV. A –4– AD5532B-1 Parameter 1 B Version 2 Unit Conditions/Comments DAC AC CHARACTERISTICS 3 Output Voltage Settling Time 22 µs max 500 pF, 5 k Ω Load Full-Scale Change OFFS_IN Settling Time 10 µs max 500 pF, 5 k Ω Load; 0 V to 3 V Step Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change Around Major Carry Digital Crosstalk 5 nV-s typ Analog Crosstalk 1 nV-s typ Digital Feedthrough 0.2 nV-s typ Output Noise Spectral Density @ 1 kHz 400 nV/ √Hz typ ISHA AC CHARACTERISTICS Output Voltage Settling Time 3 3 µs max Outputs Unloaded Acquisition Time 16 µs max AC Crosstalk 3 5nV-s typ NOTES 1See Terminology section. 2 B Version: Industrial temperature range –40 °C to +85°C; typical at +25°C. 3 Guaranteed by design and characterization, not production tested. Specifications subject to change without notice. TIMING CHARACTERISTICS PARALLEL INTERFACE Limit at TMIN, TMAX Parameter 1, 2 (B Version) Unit Conditions/Comments t1 0 ns min CS to WR Setup Time t2 0 ns min CS to WR Hold Time t3 50 ns min CS Pulsewidth Low t4 50 ns min WR Pulsewidth Low t5 20 ns min A4–A0, CAL, OFFS_SEL to WR Setup Time t6 7 ns min A4–A0, CAL, OFFS_SEL to WR Hold Time NOTES 1See Parallel Interface Timing Diagram. 2Guaranteed by design and characterization, not production tested. Specifications subject to change without notice. SERIAL INTERFACE Limit at TMIN, TMAX Parameter 1, 2 (B Version) Unit Conditions/Comments fCLKIN 3 14 MHz max SCLK Frequency t1 28 ns min SCLK High Pulsewidth t2 28 ns min SCLK Low Pulsewidth t3 15 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time t4 50 ns min SYNC Low Time t5 15 ns min DIN Setup Time t6 5 ns min DIN Hold Time t7 5 ns min SYNC Falling Edge to SCLK Rising Edge Setup Time for Readback t8 4 20 ns max SCLK Rising Edge to DOUT Valid t9 4 60 ns max SCLK Falling Edge to DOUT High Impedance t10 400 ns min 10th SCLK Falling Edge to SYNC Falling Edge for Readback t11 400 ns min 24th SCLK Falling Edge to SYNC Falling Edge for DAC Mode Write t12 5 7 ns min SCLK Falling Edge to SYNC Falling Edge for Readback NOTES 1See Serial Interface Timing Diagrams. 2Guaranteed by design and characterization, not production tested. 3In ISHA mode the maximum SCLK frequency is 20 MHz and the minimum pulsewidth is 20 ns. 4These numbers are measured with the load circuit of Figure 2. 5 SYNC should be taken low while SCLK is low for readback. Specifications subject to change without notice. AD5532B (VDD = +8 V to +16.5 V, VSS = –4.75 V to –16.5 V; AVCC = +4.75 V to +5.25 V; DVCC = +2.7 V to +5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; OFF_IN = OV; All specifications TMIN to TMAX, unless otherwise noted.) AC CHARACTERISTICS |
Nº de peça semelhante - AD5533ABC-1 |
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Descrição semelhante - AD5533ABC-1 |
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