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AD7762 Folha de dados(PDF) 5 Page - Analog Devices |
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AD7762 Folha de dados(HTML) 5 Page - Analog Devices |
5 / 28 page AD7762 Rev. 0 | Page 5 of 28 TIMING SPECIFICATIONS AVDD1 = DVDD = VDRIVE = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, TA = 25°C, normal mode, unless otherwise noted. Table 3. Parameter Limit at TMIN, TMAX Unit Description fMCLK 1 MHz min Applied master clock frequency 40 MHz max fICLK 500 kHz min Internal modulator clock derived from MCLK 20 MHz max t11, 2 0.5 × tICLK typ DRDY pulse width t2 10 ns min DRDY falling edge to CS falling edge t3 3 ns min RD/WR setup time to CS falling edge t4 (0.5 × tICLK) + 16 ns max Data access time t5 tICLK min CS low read pulse width t6 tICLK min CS high pulse width between reads t7 3 ns min RD/WR hold time to CS rising edge t8 11 ns max Bus relinquish time t9 4 × tICLK min CS low write pulse width t10 4 × tICLK min CS high period between address and data t11 5 ns min Data setup time t12 0 ns min Data hold time 1 tICLK = 1/fICLK. 2 When ICLK = MCLK, DRDY pulse width depends on the mark/space ratio of applied MCLK. TIMING DIAGRAMS DATA MSW LSW + STATUS t5 t8 t7 t6 t3 t4 t2 t1 D[0:15] CS RD/WR DRDY Figure 2. Parallel Interface Timing Diagram t9 D[0:15] CS RD/WR t10 t11 t12 REGISTER ADDRESS REGISTER DATA Figure 3. AD7762 Register Write |
Nº de peça semelhante - AD7762 |
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Descrição semelhante - AD7762 |
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