74AUP2G38GM datasheet(9/16 Pages) PHILIPS

Nome de Peças	74AUP2G38GM

Descrição Electrónicos	Low-power dual 2-input NAND gate (open-drain)

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74AUP2G38_1

Product data sheet

Rev. 01 — 16 October 2006

9 of 16

NXP Semiconductors

74AUP2G38

Low-power dual 2-input NAND gate (open-drain)

[1]

All typical values are measured at nominal VCC.

[2]

tpd is the same as tPZL and tPLZ.

[3]

CPD is used to determine the dynamic power dissipation (PD in µW).

PD =CPD × VCC2 × fi × N where:

fi = input frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching.

12. Waveforms

CL = 5 pF, 10 pF, 15 pF and 30 pF

CPD

power dissipation

capacitance

f = 1 MHz; VI = GND to VCC

[3]

VCC = 0.8 V

-

0.6

-

pF

VCC = 1.1 V to 1.3 V

-

0.7

-

pF

VCC = 1.4 V to 1.6 V

-

0.8

-

pF

VCC = 1.65 V to 1.95 V

-

0.9

-

pF

VCC = 2.3 V to 2.7 V

-

1.1

-

pF

VCC = 3.0 V to 3.6 V

-

1.4

-

pF

Table 8.

Dynamic characteristics …continued

Voltages are referenced to GND (ground=0V; for test circuit see Figure 8

Symbol Parameter

Conditions

25

°C

−40 °C to +125 °C

Unit

Min

Typ[1]

Max

Min

Max

(85

°C)

Max

(125

°C)

Measurement points are given in Table 9.

Logic levels: VOL and VOH are typical output voltage drop that occur with the output load.

Fig 7.

The data input (nA or nB) to output (nY) propagation delays

mnb132

tPLZ

VX

nY output

nA, nB input

VI

VCC

VM

VOL

GND

tPZL

VM

Table 9.

Measurement points

Supply voltage

Input

Output

VCC

VM

VX

0.8 V to 1.6 V

0.5

× V

CC

0.5

× V

CC

VOL + 0.1 V

1.65 V to 2.7 V

0.5

× VCC

0.5

× V

CC

VOL + 0.15 V

3.0 V to 3.6 V

0.5

× VCC

0.5

× V

CC

VOL + 0.3 V

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