FM8P51
Rev1.2 Mar 15, 2005
P.9/FM8P51
FEELING
TECHNOLOGY
2.1.2 TMR0 (Time Clock/Counter register)
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
01h (r/w)
TMR0
8-bit real-time clock/counter
The Timer0 is a 8-bit timer/counter. The clock source of Timer0 can come from the instruction cycle clock.
The prescaler is assigned to Timer0 by clearing the PSA bit (OPTION<3>). In this case, the prescaler will be cleared
when TMR0 register is written with a value.
2.1.3 PCL (Low Bytes of Program Counter) & Stack
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
02h (r/w)
PCL
Low order 8 bits of PC
FM8P51 devices have a 12-bit wide Program Counter (PC) and five-level deep 12-bit hardware push/pop stack. The
low byte of PC is called the PCL register. This register is readable and writable. The high byte of PC is called the
PCH register. This register contains the PC<11:8> bits and is not directly readable or writable. All updates to the
PCH register go through the PG<1:0> bits (STATUS<6:5>). As a program instruction is executed, the Program
Counter will contain the address of the next program instruction to be executed. The PC value is increased by one,
every instruction cycle, unless an instruction changes the PC.
For a GOTO instruction, the PC<9:0> is provided by the GOTO instruction word. The PC<11:10> is updated from
the PG<1:0> bits (STATUS<6:5>). The PCL register is mapped to PC<7:0>.
For a CALL instruction, the PC<9:0> is provided by the CALL instruction word. The PC<11:10> is updated from the
PG<1:0> bits (STATUS<6:5>). The next PC will be loaded (PUSHed) onto the top of STACK. The PCL register is
mapped to PC<7:0>.
For a RETIA, RETFIE, or RETURN instruction, the PC are updated (POPed) from the top of STACK. The PCL
register is mapped to PC<7:0>.
For any instruction where the PCL is the destination (excluding TBL instruction), the PC<7:0> is provided by the
instruction word or ALU result, and the PC<9:8> will be cleared. The PC<11:10> will come from the PG<1:0> bits
(STATUS<6:5>).
For TBL instruction, the PC<7:0> is provided by the ALU result, and the PC<9:8> are not changed. The PC<11:10>
will come from the PG<1:0> bits (STATUS<6:5>).
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