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MC10H130FNR2 Folha de dados(PDF) 1 Page - ON Semiconductor |
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MC10H130FNR2 Folha de dados(HTML) 1 Page - ON Semiconductor |
1 / 5 page © Semiconductor Components Industries, LLC, 2006 February, 2006 − Rev. 8 1 Publication Order Number: MC10H130/D MC10H130 Dual Latch Description The MC10H130 is a MECL 10H ™ part which is a functional/pinout duplication of the standard MECL 10K ™ family part, with 100% improvement in clock speed and propagation delay and no increase in power supply current. Features • Propagation Delay, 1.0 ns Typical • Power Dissipation, 155 mW Typical • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range) • Voltage Compensated • MECL 10K Compatible • Pb−Free Packages are Available* VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 S1 5 D1 7 CE1 6 R1 4 C 9 R2 13 CE2 11 D2 10 S2 12 Q1 Q1 Q2 Q2 2 3 14 15 Figure 1. Logic Diagram Figure 2. Pin Assignment VCC1 Q1 Q1 R1 S1 CE1 D1 VEE VCC2 Q2 Q2 R2 S2 CE2 D2 C 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 Table 1. TRUTH TABLE DC CEQn+1 L H L L L H H L L H L H L H Qn Qn Qn X X X Pin assignment is for Dual−in−Line Package. *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. CDIP−16 L SUFFIX CASE 620A MARKING DIAGRAMS* PDIP−16 P SUFFIX CASE 648 http://onsemi.com *For additional marking information, refer to Application Note AND8002/D. See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. ORDERING INFORMATION 16 1 16 1 MC10H130P AWLYYWWG 1 16 MC10H130L AWLYYWW A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G= Pb−Free Package PLLC−20 FN SUFFIX CASE 775 20 1 10H130G AWLYYWW 120 |
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