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AD5533ABC-1 Folha de dados(PDF) 1 Page - Analog Devices |
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AD5533ABC-1 Folha de dados(HTML) 1 Page - Analog Devices |
1 / 16 page REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. a AD5533B* One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 32-Channel Precision Infinite Sample-and-Hold FEATURES Infinite Sample-and-Hold Capability to 0.018% Accuracy Infinite Sample-and-Hold Total Unadjusted Error 2.5 m V High Integration: 32-Channel DAC in 12 mm 12 mm CSPBGA Per Channel Acquisition Time of 16 s Max Adjustable Voltage Output Range Output Impedance 0.5 Output Voltage Span 10 V Readback Capability DSP/Microcontroller Compatible Serial Interface Parallel Interface Temperature Range –40 C to +85 C APPLICATIONS Optical Networks Automatic Test Equipment Level Setting Instrumentation Industrial Control Systems Data Acquisition Low Cost I/O FUNCTIONAL BLOCK DIAGRAM SYNC/CS WR CAL A4 –A0 SCLK OFFSET SEL AD5533B DVCC VIN DIN DOUT ADDRESS INPUT REGISTER AVCC REF IN REF OUT OFFS IN INTERFACE CONTROL LOGIC OFFS OUT VOUT 31 VOUT 0 TRACK / RESET BUSY DAC GND AGND DGND SER / PAR VDD VSS DAC DAC DAC ADC GENERAL DESCRIPTION The AD5533B combines a 32-channel voltage translation function with an infinite output hold capability. An analog input voltage on the common input pin, VIN, is sampled and its digital represen- tation transferred to a chosen DAC register. VOUT for this DAC is then updated to reflect the new contents of the DAC register. Channel selection is accomplished via the parallel address inputs A0–A4 or via the serial input port. The output voltage range is determined by the offset voltage at the OFFS_IN pin and the gain of the output amplifier. It is restricted to a range from VSS + 2 V to VDD – 2 V because of the headroom of the output amplifier. The device is operated with AVCC = +5 V ± 5%, DVCC = +2.7 V to +5.25 V, VSS = –4.75 V to –16.5 V, and VDD = +8 V to +16.5 V and requires a stable 3 V reference on REF_IN as well as an offset voltage on OFFS_IN. PRODUCT HIGHLIGHTS 1. Precision infinite droopless sample-and-hold capability. 2. The AD5533B is available in a 74-lead CSPBGA with a body size of 12 mm 12 mm. 3. In infinite sample-and-hold mode, a total unadjusted error of ±2.5 mV is achieved by laser-trimming on-chip resistors. *Protected by U.S. Patent No. 5,969,657; other patents pending. |
Nº de peça semelhante - AD5533ABC-1 |
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Descrição semelhante - AD5533ABC-1 |
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