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AD8159-EVAL-AC Folha de dados(PDF) 1 Page - Analog Devices |
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AD8159-EVAL-AC Folha de dados(HTML) 1 Page - Analog Devices |
1 / 24 page 3.2 Gbps Quad Buffer Mux/Demux AD8159 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringements of patents or other rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. FEATURES Port level 2:1 mux/1:2 demux Each port consists of 4 lanes Each lane runs from dc to 3.2 Gbps, independent of the other lanes Compensates over 40 inches of FR4 at 3.2 Gbps through two levels of input equalization, or four levels of output pre-emphasis Accepts ac- or dc-coupled differential CML inputs Low deterministic jitter, typically 20 ps p-p Low random jitter, typically 1 ps rms BER < 10-16 On-chip termination Reversible inputs and outputs on one port Unicast or bicast on 1:2 demux function Port level loopback capability Single lane switching capability 3.3 V core supply Flexible I/O supply down to 2.5 V Low power, typically 1 W in basic configuration 100-pin TQFP_EP −40°C to +85°C operating temperature range APPLICATIONS Low cost redundancy switch SONET OC48/SDH16 and lower data rates XAUI (10 Gigabit Ethernet) over backplane Gigabit Ethernet over backplane Fibre channel 1.06 Gbps and 2.125 Gbps over backplane Infiniband over backplane PCI-Express over backplane GENERAL DESCRIPTION The AD8159 is an asynchronous, protocol agnostic, quad-lane 2:1 switch with a total of 12 differential PECL/CML-compatible inputs and 12 differential CML outputs. The operation of this product is optimized for NRZ signaling with data rates up to 3.2 Gbps per lane. Each lane offers two levels of input equalization and four levels of output pre-emphasis. The AD8159 consists of four multiplexers and four demulti- plexers, one per lane. Each port is a 4-lane link, and each lane runs up to a 3.2 Gbps data rate independent of the other lanes. The lanes are switched independently using the four select pins, SEL[3:0]; each select pin controls one lane of the port. The AD8159 has low latency and very low lane-to-lane skew. FUNCTIONAL BLOCK DIAGRAM IN_B[3:0] OUT_B[3:0] TRANSMIT PRE- EMPHASIS QUAD 2:1 MULTIPLEXER/ 1:2 DEMULTIPLEXER RECEIVE EQUALIZATION CONTROL LOGIC TRANSMIT PRE- EMPHASIS RECEIVE EQUALIZATION I/O CROSS- OVER SWITCH OUT_C[3:0]/ IN_C[3:0] IN_C[3:0]/ OUT_C[3:0] LB_A LB_B LB_C PE_A[1:0] PE_B[1:0] PE_C[1:0] EQ_A EQ_B EQ_C SEL[3:0] BICAST REVERSE_C OUT_A[3:0] IN_A[3:0] 2:1 1:2 EQ EQ EQ AD8159 Figure 1. The main application of the AD8159 is to support redundancy on both the backplane side and the line interface side of a serial link. The device has unicast and bicast capability, so it is configurable to support either 1 + 1 or 1:1 redundancy. The AD8159 supports reversing the output and input pins on one of its ports, which helps to connect two ASICs with opposite pinouts. The AD8159 is also used for testing high speed serial links by duplicating incoming data and sending it to the destination port and to test equipment simultaneously. |
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