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AD8333ACPZ-WP Folha de dados(PDF) 6 Page - Analog Devices

Nome de Peças AD8333ACPZ-WP
Descrição Electrónicos  DC to 50 MHz, Dual I/Q Demodulator and Phase Shifter
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Fabricante Electrônico  AD [Analog Devices]
Página de início  http://www.analog.com
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AD8333
Rev. A | Page 6 of 28
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
PH12
2
PH13
3
COMM
4
4LOP
5
4LON
6
LODC
7
PH23
8
PH22
24
I1PO
23
Q1PO
22
Q1NO
21
VNEG
20
COMM
19
Q2NO
18
Q2PO
17
I2PO
AD8333
TOP VIEW
(Not to Scale)
Figure 2. 32-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2,
7, 8
PH12, PH13
PH23, PH22
Quadrant Select LSB, MSB. Binary code. These logic inputs select the quadrant: 0° to 90°, 90° to180°,
180° to 270°, 270° to 360
° (see Table 4). Logic threshold is at about 1.5 V and therefore can be driven by
3 V CMOS logic (see Figure 3).
3, 20
COMM
Ground. These two pins are internally tied together.
4, 5
4LOP, 4LON
LO Inputs. No internal bias; therefore, these pins need to be biased by external circuitry. For optimum
performance, these inputs should be driven differentially with a signal level that is not less than what is
shown in Figure 22. Bias current is only −3 μA. Single-ended drive is also possible if the inputs are biased
correctly (see Figure 4).
6
LODC
Decoupling Pin for LO. A 0.1 μF capacitor should be connected between this pin and ground (see Figure 5).
9, 10,
31, 32
PH21, PH20
PH10, PH11
Phase Select LSB, MSB. Binary code. These logic inputs select the phase for a given quadrant: 0°, 22.5°, 45°, 67.5
°
(see Table 4). Logic threshold is at about 1.5 V and therefore can be driven by 3 V CMOS logic (see Figure 3).
11, 14,
27, 30
VPOS
Positive Supply. These pins should be decoupled with a ferrite bead in series with the supply, plus a 0.1 μF and
100 pF capacitor between the VPOS pins and ground. Because the VPOS pins are internally connected, one set
of supply decoupling components for all four pins should be sufficient.
12, 13,
28, 29
RF2P, RF2N
RF1N, RF1P
RF Inputs. These pins are biased internally; however, it is recommended that they be biased by dc coupling to
the output pins of the AD8332 LNA. The optimum common-mode voltage for maximum symmetrical input
differential swing is 2.5 V if ±5 V supplies are used (see Figure 6).
15
RSET
Reset for Divide-by-Four in LO Interface. Logic threshold is at about 1.5 V and therefore can be driven by
3 V CMOS logic (see Figure 3).
16, 19,
22, 25
I2NO, Q2NO
Q1NO, I1NO
Negative I/Q Outputs. These outputs are not connected for normal usage but can be used for filtering if needed.
Together with the positive I/Q outputs, they allow bypassing the internal current mirror if a lower noise output
circuit is available; VNEG needs to be tied to GND to disable the current mirror (see Figure 7).
17, 18,
23, 24
I2PO, Q2PO
Q1PO, I1PO
Positive I/Q Outputs. These outputs provide a bidirectional current that can be converted back to a voltage via
a transimpedance amplifier. Multiple outputs can be summed together by simply connecting them together.
The bias voltage should be set to 0 V or less by the transimpedance amplifier (see Figure 7).
21
VNEG
Negative Supply. This pin should be decoupled with a ferrite bead in series with the supply, plus a 0.1 μF and
100 pF capacitor between the pin and ground.
26
ENBL
Chip Enable. Logic threshold is at about 1.5 V and therefore it can be driven by 3 V CMOS logic (see Figure 3).


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