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SN74GTLPH1612 Folha de dados(PDF) 1 Page - Texas Instruments |
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SN74GTLPH1612 Folha de dados(HTML) 1 Page - Texas Instruments |
1 / 15 page www.ti.com FEATURES DGG PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 OEAB LEAB A1 A2 GND A3 VCC A4 A5 GND A6 A7 A8 GND A9 VCC A10 GND A11 A12 GND A13 A14 GND A15 VCC A16 ERC A17 A18 OEBA LEBA CEAB CLKAB B1 B2 GND B3 BIAS VCC B4 B5 GND B6 B7 B8 GND B9 VCC B10 GND B11 B12 GND B13 B14 GND B15 VREF B16 GND B17 B18 CLKBA CEBA DESCRIPTION SN74GTLPH1612 18-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE UNIVERSAL BUS TRANSCEIVER SCES287D – OCTOBER 1999 – REVISED MAY 2005 • Member of the Texas Instruments Widebus™ Family • UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes • TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes • OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference • Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels • LVTTL Interfaces Are 5-V Tolerant • High-Drive GTLP Outputs (100 mA) • LVTTL Outputs (–24 mA/24 mA) • Variable Edge-Rate Control (ERC) Input Selects GTLP Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads • Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion • Bus Hold on A-Port Data Inputs • Distributed VCC and GND Pins Minimize High-Speed Switching Noise • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) The SN74GTLPH1612 is a high-drive, 18-bit UBT™ transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, or clock-enabled modes of data transfer. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 11 Ω. GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLPH1612 is given only at the preferred higher noise margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus, UBT, TI-OPC, OEC, TI are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright © 1999–2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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