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CS5467-ISZ Folha de dados(PDF) 10 Page - Cirrus Logic |
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CS5467-ISZ Folha de dados(HTML) 10 Page - Cirrus Logic |
10 / 46 page CS5467 10 DS714A1 ADVANCE RELEASE Notes: 10. All measurements performed under static conditions. 11. If a crystal is used, XIN frequency must remain between 2.5 MHz - 5.0 MHz. If an external oscillator is used, XIN frequency range is 2.5 MHz - 20 MHz, but K must be set so that MCLK is between 2.5 MHz - 5.0 MHz. 12. If external MCLK is used, the duty cycle must be between 45% and 55% to maintain this specification. 13. The frequency of CPUCLK is equal to MCLK. 14. The minimum FSCR is limited by the maximum allowed gain register value. The maximum FSCR is limited by the full-scale signal applied to the channel input. 15. Configuration Register bits PC[6:0] are set to “0000000”. 16. The MODE pin is pulled low by an internal resistor. Low-level Input Voltage (VD = 3.3 V) All Pins Except XIN and SCLK and RESET XIN SCLK and RESET VIL - - - - - - 0.48 0.3 0.2 VD+ V V V High-level Output Voltage Iout = +5 mA VOH (VD+) - 1.0 - - V Low-level Output Voltage Iout =-5mA(VD = +5V) Iout = -2.5 mA (VD = +3.3V) VOL - - - - 0.4 0.4 V V Input Leakage Current (Note 16) Iin -±1 ±10 µA 3-state Leakage Current IOZ -- ±10 µA Digital Output Pin Capacitance Cout -5 - pF Parameter Symbol Min Typ Max Unit |
Nº de peça semelhante - CS5467-ISZ |
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Descrição semelhante - CS5467-ISZ |
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