MOTOROLA CMOS LOGIC DATA

MC14006B

28

Figure 3. Power Dissipation Test Circuit and Waveforms

PULSE

GENERATOR

VDD

14

CLOCK Q4

DP1

Q8

DP5

Q9

DP10

DP14

Q13

Q17

Q18

CL

CL

CL

CL

CL

CL

VSS

7

50

µF

ID

TEST

PRESET

8

14

9

7

1/3 MC14000

OR EQUIV

CLOCK

DATA

50%

1

f

Figure 4. Switching Time Test Circuit and Waveforms

PULSE

GENERATOR 1

PULSE

GENERATOR 2

VDD

14

CLOCK Q4

DP1

Q8

DP5

Q9

DP10

DP14

Q13

Q17

Q18

7

VSS

CL

CL

CL

CL

CL

CL

CLOCK

DATA

4–STAGE

OUTPUT

Q4, Q8

Q13, Q17

5–STAGE

OUTPUT

Q9, Q18

20 ns

20 ns

tWL

tWH

90%

50%

10%

90%

50%

10%

th “1”

tsu “1”

th “0”

tsu “0”

20 ns

20 ns

tPLH

VDD

tPHL

tTLH

tTHL

tTHL

tPHL

tTLH

VSS

VDD

VSS

VOH

VOL

VOH

VOL

Output state can change since data previously clocked in might be in either state.

90%

50%

10%

90%

50%

10%