TC9490F/FA

2001-09-03

9

3.

DATA, CLCK Input/Output Timing

(1)

CLCK input mode (regardless of setting of HS and UHS bits of SPEED command)

Characteristics

Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

“H” level

tHW

¾

50

¾

¾

Clock pulse width

“L” level

tLW

¾

50

¾

¾

Input setup time

tSU

¾

400

¾

¾

Transfer time (1)

“L” level

tpHL1

¾

¾

¾

5

“H” level

tpLH2

¾

¾

¾

15

Transfer time (2)

“L” level

tpHL2

¾

CLCK input mode

¾

¾

15

ns

(2)

CLCK output mode (tHW, tLW, tpLH3 only, ´ 1/n at ´n speed)

Characteristics

Symbol

Test

Circuit

Test Condition

Min

Typ.

Max

Unit

“H” level

tHW

¾

¾

¾

950

Clock pulse width

“L” level

tLW

¾

¾

¾

950

Transfer time (1)

“L” level

tpHL1

¾

¾

¾

5

“H” level

tpLH2

¾

¾

¾

15

Transfer time (2)

“L” level

tpHL2

¾

¾

¾

15

Transfer time (3)

“H” level

tpLH3

¾

CLCK output mode

¾

¾

850

ns

SUBQ

SUBP

SFSY

CLCK

DATA

tpHL1

tpHL2

tHW

tSU

tLW

tpLH2

SUBQ

SUBP

SFSY

CLCK

DATA

tpHL1

tpHL2

tHW

tpLH3

tLW

tpLH2