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MC10EP445FAR2 Folha de dados(PDF) 11 Page - ON Semiconductor |
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MC10EP445FAR2 Folha de dados(HTML) 11 Page - ON Semiconductor |
11 / 18 page MC10EP445, MC100EP445 http://onsemi.com 11 Similarly, for CKSEL HIGH operation, the data is latched only on the rising edge of the clock and the time from when the serial data is latched À to when the data is seen on the parallel outputÁ is 12 clock cycles (see Figure 8). Figure 8. Timing Diagram A. 1:8 Serial to Parallel Conversion with CKSEL HIGH CLK SINA RESET CKSEL PCLK Q0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 Q1 Q2 Q3 Q4 Q5 Q6 Q7 D0 D1 D2 D3 D4 D5 D6 D7 CKEN 123 4 5 6 Á À Number of Clock Cycles from Data Latch to Q 7 8 9 10 11 12 |
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