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CAT5126 Folha de dados(PDF) 4 Page - Catalyst Semiconductor

Nome de Peças. CAT5126
descrição  One-Time Digitally Programmable 32 Tap Potentiometer
Download  11 Pages
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Fbricantes  CATALYST [Catalyst Semiconductor]
Página de início  http://www.catalyst-semiconductor.com
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CAT5126 Folha de dados(HTML) 4 Page - Catalyst Semiconductor

 
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CAT5126
Doc. No. 2129 Rev. A
4
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ELECTRICAL CHARACTERISTICS (continued)
VDD = 2.5V to 5.5V, VPP = GND, VH = VDD, VL = GND, TA = -40°C to +85°C, unless otherwise noted. Typical values
are at VDD = 5.0V, TA = +25°C, unless otherwise noted.
(1)
TIMING CHARACTERISTICS
(2)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tCU
U/D
¯ Mode to CS
¯¯¯ Setup
Figures 1, 2
50
ns
tCI
CS
¯¯¯ Hold to U/D
¯ Mode
Figures 1, 2
50
ns
tIC
U/D
¯ Step Hold to CS
¯¯¯
Figures 1, 2
0
ns
tIL
U/D
¯ Step Low Time
Figures 1, 2
100
ns
tIH
U/D
¯ Step High Time
Figures 1, 2
100
ns
tIW
Wiper Switching Time
CL = 0pF, Figures 1, 2
100
ns
tPC
VPP Rising Edge to CS
¯¯¯
Falling Edge
Figure 3
1
ms
tCP
CS
¯¯¯ Falling Edge to VPP
Falling Edge
Figure 3
5
ms
tCL
CS
¯¯¯ Step Low Time
Figure 3
5
ms
tCH
CS
¯¯¯ Step High Time
Figure 3
5
ms
tPH
VPP Falling Edge to CS
¯¯¯
Rising Edge
Figure 3
1
ms
fU/D¯MAX
U/D
¯ Frequency
5
MHz
tUP
Power-Up Time
(Note 3)
1
ms
100kΩ variable resistor
configuration, CL = 10pF
1
tSETTLE
Output Settling Time
100kΩ potentiometer
configuration, CL = 10pF
0.25
µs
Notes:
(1) All devices are production tested at TA = +25°C and are guaranteed by design for TA = -40°C to +85°C.
(2) Digital timing is guaranteed by design, not production tested.
(3) Power-up time is the period of time from when the power supply is applied until the serial interface is ready for writing.


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