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CAT24C208 Folha de dados(PDF) 8 Page - Catalyst Semiconductor |
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CAT24C208 Folha de dados(HTML) 8 Page - Catalyst Semiconductor |
8 / 13 page CAT24C208 8 Doc. No. 1044, Rev. F © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice Figure 7. Random Access Read T R A T S0 0 0 0 0 1 1 0K C AS x x x x x x 1S0 S S E R D D A t n e m g e SK C A T R A T S0 0 0 0 0 1 0 1K C AS S E R D D A 0 A - 7 AK C AT R A T S1 0 0 0 0 1 0 1K C AA T A DK C A O NP O T S Figure 8. Sequential Read T R A T S0 0 0 0 0 1 1 0K C AS x x x x x x 1S0 S S E R D D A t n e m g e SK C A T R A T S0 0 0 0 0 1 0 1K C AS S E R D D A 0 A - 7 AK C AT R A T S1 0 0 0 0 1 0 1K C A0 A T A DK C A. . . . . .N A T A DK C A O NP O T S Figure 9. Byte Write T R A T S0 0 0 0 0 1 1 0K C AS x x x x x x 1S0 S S E R D D A t n e m g e SK C A T R A T S0 0 0 0 0 1 0 1K C AS S E R D D A 0 A - 7 AK C AA T A DK C AP O T S Figure 10. Page Write T R A T S0 0 0 0 0 1 1 0K C AS x x x x x x 1S0 S S E R D D A t n e m g e SK C A T R A T S0 0 0 0 0 1 0 1K C AS S E R D D A 0 A - 7 AK C A0 A T A DK C A. . . . . . . . . .5 1 A T A DK C AP O T S The segment pointer is at the address 60h and is write- only. This means that a memory access at 61h will give undefined results. The segment pointer is a volatile register. The device configuration register at 62/63 (hex) is a non-volatile register. The configuration register will be shipped in the erased (set to FFh) state. The segment pointer is used to expand the available DDC address space while maintaining backward com- patibility with older DDC interfaces such as DDC2B. For each value of the 8-bit segment pointer one segment (256 bytes) is available at the A0/A1 pair. The standard DDC 8-bit address is sufficient to address each of the 256 bytes within a segment. Note that if the segment pointer is set to 00h then the device will behave like a standard DDC2B EEPROM. Read and write with segment pointer can expand the addressable memory to 512 bytes in each bank with wraparound to the next segment in the same bank only. The two banks can be individually selected by the configuration register and EDID Sel pin, as shown in figure 19. The segments are selected by the two bits S 1S0 = 00 or 01 in the segment address. Figures 7 to 10 show the random read, sequential read, byte write and page write. |
Nº de peça semelhante - CAT24C208 |
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Descrição semelhante - CAT24C208 |
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