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CAT24C208WI-GT3 Folha de dados(PDF) 5 Page - Catalyst Semiconductor |
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CAT24C208WI-GT3 Folha de dados(HTML) 5 Page - Catalyst Semiconductor |
5 / 13 page CAT24C208 5 Doc No. 1044, Rev. F © 2006 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice FUNCTIONAL DESCRIPTION The CAT24C208 has a total memory space of 1K bytes which is accessible from either of two I2C interface ports, (DSP_SDA and DSP_SCL) or (DDC_SDA and DDC_SCL), and with the use of segment pointer at address 60h. On power up and after any instruction, the segment pointer will be in segment 00h for DSP and in segment 00h of the bank selected by the configuration register for DDC. The entire memory appears as contiguous memory space from the perspective of the display interface (DSP_SDA and DSP_SCL), see Table 2, and Figures 11 to Figure 18 for a complete description of the DSP Interface. A configuration register at addresses 62/63h is used to configure the operation and memory map of the device as seen from the DDC interface, (DDC_SDA and DDC_SCL). Read and write operations can be performed on any location within the memory space from the display DSP interface regardless of the state of the EDID SEL pin or the activity on the DDC interface. From the DDC interface, the memory space appears as two 512 byte banks of memory, with 2 segments each 00h and 01h in the upper and lower bank, see Table 1. Each bank of memory can be used to store an E-EDID data structure. However, only one bank can be read through the DDC port at a time. The active bank of memory (that is, the bank that appears at address A0h on the DDC port) is controlled through the configuration register at 62/63h and the EDID_SEL pin. No write operations are possible from the DDC interface unless the DDC Write Enable bit is set (WE = 1) in the device configuration register at device address 62h. The device automatically arbitrates between the two interfaces to allow the appearance of individual access to the memory from each interface. In a typical E-EDID application the EDID_SEL pin is usually connected to the “Analog Cable Detect” pin of a VESA M1 compliant, dual-mode (analog and digital) display. In this manner, the E-EDID appearing at ad- dress A0h on the DDC port will be either the analog or digital E-EDID, depending on the state of the “Analog Cable Detect” pin (pin C3 of the M1-DA connector). See Figure 1. Figure 1. TO HOST CONTROLLER 28 27 8 HPD FUSE, RESISTOR OR OTHER CURRENT LIMITING DEVICE REQUIRED IN ALL M1 DISPLAYS 2A MAX RELAY CONTACTS SHOWN IN DE-ENERGIZED POSITION E-EDID EEPROM 8 7 6 5 DDC +5V DDC CLK DDC DATA 26 C3 47.5K 10K 1 2 3 4 I2C TO PROJECTOR/MONITOR DISPLAY CONTROLLER +5V DC (SUPPLIED BY DISPLAY) Segment 1 256 Bytes Segment 0 256 Bytes Segment 1 256 Bytes Segment 0 256 Bytes Segment 3 256 Bytes Segment 2 256 Bytes Segment 1 256 Bytes Segment 0 256 Bytes 01 00 01 00 11 10 01 00 00 00 00 Segment Pointer No Segment Pointer Segment Pointer No Segment Pointer Lower Bank Upper Bank Address by Configuration Register (see Figure 19) MEMORY ARRAY MEMORY ARRAY Table 1: DDC Interface Table 2: DSP Interface |
Nº de peça semelhante - CAT24C208WI-GT3 |
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Descrição semelhante - CAT24C208WI-GT3 |
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