© Semiconductor Components Industries, LLC, 2006

November, 2006 − Rev. 9

1

Publication Order Number:

MC100LVEP34/D

MC100LVEP34

2.5V / 3.3VECL ÷2, ÷4, ÷8

Clock Generation Chip

The MC100LVEP34 is a low skew ÷2, ÷4, ÷8 clock generation chip

designed explicitly for low skew clock generation applications. The

internal dividers are synchronous to each other, therefore, the common

generated voltage supply, is available to this device only. For

single−ended input conditions, the unused differential input is

0.01

mF capacitor and limit current sourcing or sinking to 0.5 mA.

The common enable (EN) is synchronous so that the internal

dividers will only be enabled/disabled when the internal clock is

already in the LOW state. This avoids any chance of generating a runt

clock pulse on the internal clock when the device is enabled/disabled

as can happen with an asynchronous control. An internal runt pulse

could lead to losing synchronization between the internal divider

stages. The internal enable flip−flop is clocked on the falling edge of

the input clock; therefore, all associated specification limits are

referenced to the negative edge of the clock input.

Upon start−up, the internal flip−flops will attain a random state; the

master reset (MR) input allows for the synchronization of the internal

dividers, as well as multiple LVEP34s in a system. Single−ended CLK

−3.0 V in NECL mode.

Features

SO−16

D SUFFIX

CASE 751B

1

16

MARKING

DIAGRAMS*

A

= Assembly Location

L, WL

= Wafer Lot

Y

= Year

W, WW = Work Week

G or G = Pb−Free Package

1

16

100LVEP34G

AWLYWW

TSSOP−16

DT SUFFIX

CASE 948F

*For additional marking information, refer to

Application Note AND8002/D.

http://onsemi.com

1

16

100

VP34

ALYWG

G

1

16

See detailed ordering and shipping information in the package

dimensions section on page 8 of this data sheet.

ORDERING INFORMATION

(Note: Microdot may be in either location)