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MC10135 Folha de dados(PDF) 1 Page - ON Semiconductor |
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MC10135 Folha de dados(HTML) 1 Page - ON Semiconductor |
1 / 8 page LOGIC DIAGRAM VCC1 = PIN 1 VCC2 = PIN 16 VEE = PIN 8 S1 5 J1 7 K1 6 R1 4 C 9 S2 12 J2 10 K2 11 R2 13 Q1 Q1 Q2 Q2 2 3 15 14 DIP PIN ASSIGNMENT VCC1 Q1 Q1 R1 S1 K1 J1 VEE VCC2 Q2 Q2 R2 S2 K2 J2 C 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 Pin assignment is for Dual–in–Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 18 of the ON Semiconductor MECL Data Book (DL122/D). © Semiconductor Components Industries, LLC, 2002 January, 2002 – Rev. 7 1 Publication Order Number: MC10135/D MC10135 Dual J-K Master-Slave Flip-Flop The MC10135 is a dual master–slave dc coupled J–K flip–flop. Asynchro– nous set (S) and reset (R) are provided. The set and reset inputs override the clock. A common clock is provided with separate J–K inputs. When the clock is static, the J–K inputs do not effect the output. The output states of the flip–flop change on the positive transition of the clock. • P D = 280 mW typ/pkg (No Load) • f Tog = 140 MHz typ • t pd = 3.0 ns typ • t r, tf = 2.5 ns typ (20%–80%) R–S TRUTH TABLE CLOCK J–K TRUTH TABLE* R S Qn+1 J K Qn+1 L L H H L H L H Qn H L N.D. L H L H L L H H Qn L H Qn N.D. = Not Defined * Output states change on positive transition of clock for J–K input condition present. http://onsemi.com Device Package Shipping ORDERING INFORMATION MC10135L CDIP–16 25 Units / Rail MC10135P PDIP–16 25 Units / Rail MC10135FN PLCC–20 46 Units / Rail MARKING DIAGRAMS 1 16 A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week CDIP–16 L SUFFIX CASE 620 MC10135L AWLYYWW PDIP–16 P SUFFIX CASE 648 PLCC–20 FN SUFFIX CASE 775 10135 AWLYYWW 1 1 16 MC10135P AWLYYWW |
Nº de peça semelhante - MC10135 |
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Descrição semelhante - MC10135 |
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