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CAT523 Folha de dados(PDF) 5 Page - Catalyst Semiconductor

Nome de Peças. CAT523
descrição  Configured Digitally Programmable Potentiometer
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Fbricantes  CATALYST [Catalyst Semiconductor]
Página de início  http://www.catalyst-semiconductor.com
Logo CATALYST - Catalyst Semiconductor

CAT523 Folha de dados(HTML) 5 Page - Catalyst Semiconductor

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CAT523
5
Doc. No. 2005, Rev. E
DPP addressing is as follows:
DPP OUTPUT
A0
A1
VOUT1
0
0
VOUT2
1
0
PIN DESCRIPTION
Pin
Name
Function
1VDD
Power supply positive.
2
CLK
Clock input pin.Clock input pin.
3
RDY/
BSY
Ready/Busy Output
4
CS
Chip Select
5
DI
Serial data input pin.
6
DO
Serial data output pin.
7
PROG
EEPROM Programming Enable
Input
8
GND
Power supply ground.
9VREFL
Minimum DPP output voltage.
10
NC
No Connect.
11
NC
No Connect.
12
VOUT2
DPP output channel 2.
13
VOUT1
DPP output channel 1.
14
VREFH
Maximum DPP output voltage.
DEVICE OPERATION
The CAT523 is a dual 8-bit configured digitally
programmable potentiometer (DPP) whose outputs can
be programmed to any one of 256 individual voltage
steps. Once programmed, these output settings are
retained in non-volatile memory and will not be lost
when power is removed from the chip. Upon power up
the DPPs return to the settings stored in non-volatile
memory. Each DPP can be written to and read from
independently without effecting the output voltage during
the read or write cycle.
Each output can also be
temporarily adjusted without changing the stored output
setting, which is useful for testing new output settings
before storing them in memory.
DIGITAL INTERFACE
The CAT523 employs a 3 wire, Microwire-like, serial
control interface consisting of Clock (CLK), Chip Select
(CS) and Data In (DI) inputs. For all operations, address
and data are shifted in LSB first. In addition, all digital
data must be preceded by a logic “1” as a start bit. The
DPP address and data are clocked into the DI pin on the
clock’s rising edge. When sending multiple blocks of
information a minimum of two clock cycles is required
between the last block sent and the next start bit.
Multiple devices may share a common input data line by
selectively activating the CS control of the desired IC.
Data Outputs (DO) can also share a common line
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
CHIP SELECT
Chip Select (CS) enables and disables the CAT523’s
read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is
active. Data loaded into the DPP control registers will
remain in effect until CS goes low. Bringing CS to a logic
low returns all DPP outputs to the settings stored in non-
volatile memory and switches DO to its high impedance
Tri-State mode.
Because CS functions like a reset the CS pin has been
equipped with a 30 ns to 90 ns filter circuit to prevent
noise spikes from causing unwanted resets and the loss
of volatile data.
CLOCK
The CAT523’s clock controls both data flow in and out of
the IC and non-volatile memory cell programming. Serial
data is shifted into the DI pin and out of the DO pin on the
clock’s rising edge. While it is not necessary for the clock
to be running between data transfers, the clock must be
operating in order to write to non-volatile memory, even
though the data being saved may already be resident in
the DPP wiper control register.
No clock is necessary upon system power-up. The
CAT523’s internal power-on reset circuitry loads data
from non-volatile memory to the DPPs without using the
external clock.
As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking data
into the control registers. Standard CMOS and TTL logic
families work well in this regard and it is recommended
that any mechanical switches used for breadboarding or
device evaluation purposes be debounced by a flip-flop
or other suitable debouncing circuit.


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