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NBSG14 Folha de dados(PDF) 9 Page - ON Semiconductor

Nome de Peças NBSG14
Descrição Electrónicos  2.5V/3.3V SiGe Differential 1:4 Clock/Data Driver with RSECL Outputs
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Fabricante Electrônico  ONSEMI [ON Semiconductor]
Página de início  http://www.onsemi.com
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NBSG14
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Table 9. AC CHARACTERISTICS for QFN−16
VCC = 0 V; VEE = −3.465 V to −2.375 V or VCC = 2.375 V to 3.465 V; VEE = 0 V
Symbol
Characteristic
−40
°C
25
°C
85
°C
Unit
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
fmax
Maximum Frequency
(See Figure 4) (Note 29)
10.5
12
10.5
12
10.5
12
GHz
tPLH,
tPHL
Propagation Delay to
Output Differential
90
125
160
90
125
160
90
125
160
ps
tSKEW
Duty Cycle Skew (Note 30)
Within−Device Skew (Note 31)
Device−to−Device Skew (Note 32)
3
6
25
15
15
50
3
6
25
15
15
50
3
6
25
15
15
50
ps
tJITTER
RMS Random Clock Jitter
(Figure 4) (Note 34)
fin < 10 GHz
Peak−to−Peak Data Dependent Jitter
(Note 35)
fin < 10 Gb/s
0.2
1
0.2
10
1
0.2
1
ps
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 33)
75
2600
75
2600
75
2600
mV
tr
tf
Output Rise/Fall Times
Q, Q
(20% − 80%) @ 1 GHz
15
30
55
20
30
55
20
30
55
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
29. Measured using a 500 mV source, 50% duty cycle clock source. All outputs loaded with 50
W to VCC − 2.0 V. Input edge rates 40 ps
(20% − 80%)
30. See Figure 6. tSKEW = |tPLH − tPHL| for a nominal 50% Differential Clock Input Waveform.
31. Within−Device skew is measured between outputs under identical transitions and conditions on any one device.
32. Device−to−device skew for identical transitions at identical VCC levels.
33. VINPP (MAX) cannot exceed VCC − VEE (applicable only when VCC−VEE < 2600 mV).
34. Additive RMS Jitter with 50% duty cycle clock signal at 10 GHz.
35. Additive Peak−to−Peak data dependent jitter with NRZ PRBS 231−1 data at 10 Gb/s.


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