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NBSG16VSBAEVB Folha de dados(PDF) 3 Page - ON Semiconductor |
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3 / 14 page NBSG16VS http://onsemi.com 3 50 W 50 W VTD D D VTD VMM Q Q VBB VEE VCC Figure 3. Logic Diagram/ Voltage Source Implementation 75 K W 75 K W 36.5 K W VCTRL Q OUT 50 W 50 W VCC − 2 V VCTRL + VCC Q OUT Figure 4. Alternative Voltage Source Implementation 50 W 50 W VTD D D VTD VMM Q Q VBB VEE VCC 75 K W 75 K W 36.5 K W VCTRL 140 W 140 W +3.3 V 0.1 mF Q OUT Q OUT RVAR Table 2. INTERFACING OPTIONS INTERFACING OPTIONS CONNECTIONS CML Connect VTD and VTD to VCC LVDS Connect VTD and VTD Together AC−COUPLED Bias VTD and VTD Inputs within Common Mode Range (VIHCMR) RSECL, PECL, NECL Standard ECL Termination Techniques LVTTL An external voltage should be applied to the unused complementary differential input. Nominal voltage is 1.5 V for LVTTL. LVCMOS VMM should be connected to the unused complementary differential input. |
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