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ADF4113HVBRUZ Folha de dados(PDF) 6 Page - Analog Devices |
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ADF4113HVBRUZ Folha de dados(HTML) 6 Page - Analog Devices |
6 / 20 page ADF4113HV Rev. 0 | Page 6 of 20 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 CP CPGND AGND AVDD RFINA RFINB RSET REFIN 16 15 14 13 12 11 10 9 DVDD MUXOUT LE CE DGND CLK DATA VP ADF4113HV TOP VIEW (Not to Scale) Figure 3. TSSOP Pin Configuration PIN 1 INDICATOR 1 CPGND 2 AGND 3 AGND 4 RFINB 5 RFINA 13 DATA 14 LE 15 MUXOUT 12 CLK 11 CE ADF4113HV TOP VIEW (Not to Scale) Figure 4. LFCSP Pin Configuration Table 5. Pin Function Descriptions TSSOP Pin No. LFCSP Pin No. Mnemonic Description 1 19 RSET Connecting a resistor between this pin and CPGND sets the maximum charge pump output current. The nominal voltage potential at the RSET pin is 0.56 V for the ADF4113HV. The relationship between ICP and RSET is ICPmax = 3/RSET. Therefore, with RSET = 4.7 kΩ, ICPmax = 640 μA. 2 20 CP Charge Pump Output. When enabled, this pin provides ±ICP to the external loop filter; in turn, this drives the external VCO. 3 1 CPGND Charge Pump Ground. CPGND is the ground return path for the charge pump. 4 2, 3 AGND Analog Ground. This is the ground return path of the prescaler. 5 4 RFINB Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. 6 5 RFINA Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO. 7 6, 7 AVDD Analog Power Supply. The power supply can range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD. 8 8 REFIN Reference Input. This pin is a CMOS input with a nominal threshold of VDD/2, and an equivalent input resistance of 100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or can be ac-coupled. 9 9, 10 DGND Digital Ground. 10 11 CE Chip Enable. A Logic low on this pin powers down the device and puts the charge pump output into three-state mode. Taking the pin high powers up the device depending on the status of the Power-Down Bit PD1. 11 12 CLK Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. 12 13 DATA Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. 13 14 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches; the latch is selected using the control bits. 14 15 MUXOUT Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference frequency to be externally accessed. 15 16, 17 DVDD Digital Power Supply. This can range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground plane (1μF, 1nF) should be placed as close as possible to this pin. For best performance, the 1 μF capacitor should be placed within 2 mm of the pin. The placing of the 1nF capacitor is less critical but should still be within 5 mm of the pin. DVDD must have the same value as AVDD. 16 18 VP Charge Pump Power Supply. VP can range from 13.5 V to 16.5 V and should be decoupled appropriately. |
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