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TSC80251G2D-24IB Folha de dados(PDF) 7 Page - ATMEL Corporation |
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TSC80251G2D-24IB Folha de dados(HTML) 7 Page - ATMEL Corporation |
7 / 77 page 7 AT/TSC8x251G2D 4135F–8051–11/06 Signals Table 2. Product Name Signal Description Signal Name Type Description Alternate Function A17 O 18 th Address Bit Output to memory as 18th external address bit (A17) in extended bus applications, depending on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 20). P1.7 A16 O 17 th Address Bit Output to memory as 17th external address bit (A16) in extended bus applications, depending on the values of bits RD0 and RD1 in UCONFIG0 byte (see Table 13, Page 20). P3.7 A15:8(1) O Address Lines Upper address lines for the external bus. P2.7:0 AD7:0(1) I/O Address/Data Lines Multiplexed lower address lines and data for the external memory. P0.7:0 ALE O Address Latch Enable ALE signals the start of an external bus cycle and indicates that valid address information are available on lines A16/A17 and A7:0. An external latch can use ALE to demultiplex the address from address/data bus. – AWAIT# I Real-time Asynchronous Wait States Input When this pin is active (low level), the memory cycle is stretched until it becomes high. When using the Product Name as a pin-for-pin replacement for a 8xC51 product, AWAIT# can be unconnected without loss of compatibility or power consumption increase (on-chip pull-up). Not available on DIP package. – CEX4:0 I/O PCA Input/Output pins CEXx are input signals for the PCA capture mode and output signals for the PCA compare and PWM modes. P1.7:3 EA# I External Access Enable EA# directs program memory accesses to on-chip or off-chip code memory. For EA# = 0, all program memory accesses are off-chip. For EA# = 1, an access is on-chip ROM if the address is within the range of the on-chip ROM; otherwise the access is off-chip. The value of EA# is latched at reset. For devices without ROM on-chip, EA# must be strapped to ground. – ECI O PCA External Clock input ECI is the external clock input to the 16-bit PCA timer. P1.2 MISO I/O SPI Master Input Slave Output line When SPI is in master mode, MISO receives data from the slave peripheral. When SPI is in slave mode, MISO outputs data to the master controller. P1.5 MOSI I/O SPI Master Output Slave Input line When SPI is in master mode, MOSI outputs data to the slave peripheral. When SPI is in slave mode, MOSI receives data from the master controller. P1.7 INT1:0# I External Interrupts 0 and 1 INT1#/INT0# inputs set IE1:0 in the TCON register. If bits IT1:0 in the TCON register are set, bits IE1:0 are set by a falling edge on INT1#/INT0#. If bits IT1:0 are cleared, bits IE1:0 are set by a low level on INT1#/INT0#. P3.3:2 |
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