Os motores de busca de Datasheet de Componentes eletrônicos |
|
CS82C50A-5 Folha de dados(PDF) 9 Page - Intersil Corporation |
|
CS82C50A-5 Folha de dados(HTML) 9 Page - Intersil Corporation |
9 / 25 page 9 FN2958.5 August 24, 2006 82C50A The contents of the Line Status Register are indicated in the above table and are described below. LSR(0) Data Ready (DR): Data Ready is set high when an incoming character has been received and transferred into the Receiver Buffer Register. LSR(0) is reset low by a CPU read of the data in the Receiver Buffer Register. LSR(1) Overrun Error (OE): Overrun Error indicates that data in the Receiver Buffer Register was not read by the CPU before the next character was transferred into the Receiver Buffer Register, overwriting the previous character. The OE indicator is reset whenever the CPU reads the contents of the Line Status Register. LSR(2) Parity Error (PE): Parity Error indicates that the received data character does not have the correct even or odd parity, as selected by the Even Parity Select bit (LCR (4)). The PE bit is set high upon detection of a parity error, and is reset low when the CPU reads the contents of the LSR. LSR(3) Framing Error (FE): Framing Error indicates that the received character did not have a valid stop bit. LSR(3) is set high when the stop bit following the last data bit or parity bit is detected as a zero bit (spacing level). The FE indicator is reset low when the CPU reads the contents of the LSR. LSR(4) Break Interrupt (BI): Break Interrupt is set high when the received data input is held in the spacing (logic 0) state for longer than a full word transmission time (start bit + data bits + parity + stop bits). The B indicator is reset when the CPU reads the contents of the Line Status Register. LSR(1) - LSR(4) are the error conditions that produce a Receiver Line Status interrupt (priority 1 interrupt in the Interrupt Identification Register (IIR)) when any of the conditions are detected. This interrupt is enabled by setting lER (2) = 1 in the Interrupt Enable Register. LSR(5) Transmitter Holding Register Empty (THRE): THRE indicates that the 82C50A is ready to accept a new character for transmission. The THRE bit is set high when a character is transferred from the Transmitter Holding Register into the Transmitter Shift Register. LSR(5) is reset low by the loading of the Transmitter Holding Register by the CPU. LSR(5) is not reset by a CPU read of the LSR. When the THRE interrupt is enabled (IER(1) = 1), THRE causes a priority 3 interrupt in the lIR. If THRE is the interrupt source indicated in IIR, lNTRPT is cleared by a read of the IIR. LSR(6) Transmitter Empty (TEMT): TEMT is set high when the Transmitter Holding Register (THR) and the Transmitter Shift Register (TSR) are both empty. LSR(6) is reset low when a character is loaded into the THR and remains low until the character is transferred out of SOUT. TEMT is not reset low by a CPU read of the LSR. LSR(7): This bit is permanently set to logic 0. MODEM CONTROL REGISTER (MCR) The MCR controls the interface with the modem or data set as described below. The MCR can be written and read. The RTS, DTR, OUT1 and OUT2 outputs are directly controlled by their control bits in this register. A high input asserts a low (true) at the output pins. MCR(0): When MCR(0) is set high, the DTR output is forced low. When MCR(0) is reset low, the DTR output is forced high. The DTR output of the 82C50A may be input into an ElA inverting line driver as the 1488 to obtain the proper polarity input at the modem or data set. MCR(1): When MCR(1) is set high, the RTS output is forced low. When MCR(1) is reset low, the RTS output is forced high. The RTS output of the 82C50A may be input into an ElA inverting line driver as the 1488 to obtain the proper polarity input at the modem or data set. MCR(2): When MCR(2) is set high, the OUT1 output is forced low. When MCR(2) is reset low, the OUT1 output is forced high. OUT1 is an user designated output. LSR BITS 0 THRU 7 LOGIC 1 LOGIC 0 LSR (0) Data Ready (DR) Ready Not Ready LSR (1) Overrun Error (OE) Error No Error LSR (2) Parity Error (PE) Error No Error LSR (3) Framing Error (FE) Error No Error LSR (4) Break Interrupt (BI) Break No Break LSR (5) Transmitter Holding Register Empty (THRE) Empty Not Empty LSR (6) Transmitter Empty (TEMT) Empty Not Empty LSR (7) Not Used MCR BITS 0 THRU 7 MCR BIT LOGIC 1 MCR BIT LOGIC 0 MCR (0) Data Terminal Ready (DTR) DTR Output Low DTR Output High MCR (1) Request to Send (RTS) RTS Output Low RTS Output High MCR (2) OUT1 OUT1 Output Low OUT1 Output High MCR (3) OUT2 OUT2 Output Low OUT2 Output High MCR (4) LOOP LOOP Enabled LOOP Disabled MCR (5) 0 MCR (6) 0 MCR (7) 0 |
Nº de peça semelhante - CS82C50A-5 |
|
Descrição semelhante - CS82C50A-5 |
|
|
Ligação URL |
Privacy Policy |
ALLDATASHEETPT.COM |
ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |