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CA3306A Folha de dados(PDF) 11 Page - Intersil Corporation |
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CA3306A Folha de dados(HTML) 11 Page - Intersil Corporation |
11 / 17 page 11 Device Operation A sequential parallel technique is used by the CA3306 converter to obtain its high speed operation. The sequence consists of the “Auto Balance” phase φ1 and the “Sample Unknown” phase φ2. (Refer to the circuit diagram.) Each conversion takes one clock cycle (see Note). With the phase control low, the “Auto Balance” ( φ1) occurs during the High period of the clock cycle, and the “Sample Unknown” ( φ2) occurs during the low period of the clock cycle. During the “Auto Balance” phase, a transmission-gate switch is used to connect each of 64 commutating capacitors to their associated ladder reference tap. Those tap voltages will be as follows: VTAP (N) = [(VREF/64) x N] - [VREF/(2 x 64)] = VREF[(2N - 1)/126], Where: VTAP (N) = reference ladder tap voltage at point N, VREF = voltage across VREF- to VREF+, N = tap number (I through 64). NOTE: This device requires only a single-phase clock The terminology of φ1 and φ2 refers to the High and Low periods of the same clock. The other side of the capacitor is connected to a single- stage inverting amplifier whose output is shorted to its input by a switch. This biases the amplifier at its intrinsic trip point, which is approximately, (VDD - VSS)/2. The capacitors now charge to their associated tap voltages, priming the circuit for the next phase. In the “Sample Unknown” phase, all ladder tap switches are opened, the comparator amplifiers are no longer shorted, and VlN is switched to all 64 capacitors. Since the other end of the capacitor is now looking into an effectively open cir- cuit, any voltage that differs from the previous tap voltage will appear as a voltage shift at the comparator amplifiers. All comparators whose tap voltages were lower than VlN will drive the comparator outputs to a “low” state. All compara- tors whose tap voltages were higher than VlN will drive the comparator outputs to a “high” state. A second, capacitor- coupled, auto-zeroed amplifier further amplifies the outputs. The status of all these comparator amplifiers are stored at the end of this phase ( φ2), by a secondary latching amplifier stage. Once latched, the status of the 64 comparators is decoded by a 64-bit 7-bit decode array and the results are clocked into a storage register at the rising edge of the next φ2. A three-state buffer is used at the output of the 7 storage registers which are controlled by two chip-enable signals. CE1 will independently disable 81 through 86 when it is in a high state. CE2 will independently disable B1 through B6 and the OF buffers when it is in the low state (Table 1). To facilitate usage of this device a phase-control input is provided which can effectively complement the clock as it enters the chip. Also, an on-board zener is provided for use as a reference voltage. Continuous Clock Operation One complete conversion cycle can be traced through the CA3306 via the following steps. (Refer to timing diagram, Figure 1.) With the phase control in a “High” state, the rising edge of the clock input will start a “sample” phase. During this entire “High” state of the clock, the 64 comparators will track the input voltage and the 64 latches will track the comparator outputs. At the falling edge of the clock, after the specified aperture delay, all 64 comparator outputs are captured by the 64 latches. This ends the “sample” phase and starts the “auto balance” phase for the comparators. During this “Low” state of the clock the output of the latches propagates through the decode array and a 7-bit code appears at the D inputs of the output registers. On the next rising edge of the clock, this 7- bit code is shifted into the output registers and appears with time delay to as valid data at the output of the three-state drivers. This also marks the start of a new “sample” phase, thereby repeating the conversion process for this next cycle. Pulse Mode Operation For sampling high speed nonrecurrent or transient data, the converter may be operated in a pulse mode in one of three ways. The fastest method is to keep the converter in the Sample Unknown phase, φ2, during the standby state. The device can now be pulsed through the Auto Balance phase with a single pulse. The analog value is captured on the leading edge of φ1 and is transferred into the output registers on the trailing edge of φ1. We are now back in the standby state, φ2, and another conversion can be started, but not later than 5 µs due to the eventual droop of the commutating capacitors. Another advantage of this method is that it has the potential of having the lowest power drain. The larger the time ratio between φ2 and φ1, the lower the power consump- tion. (See Timing Waveform, Figure 3.) The second method uses the Auto Balance phase, φ1, as the standby state. In this state the converter can stay indefi- nitely waiting to start a conversion. A conversion is per- formed by strobing the clock input with two φ2 pulses. The first pulse starts a Sample Unknown phase and captures the analog value in the comparator latches on the trailing edge. A second φ2 pulse is needed to transfer the data into the out- put registers. This occurs on the leading edge of the second pulse. The conversion now takes slightly longer, but the rep- etition rate may be as slow as desired. The disadvantage to this method is the higher device dissipation due to the low ratio of φ2 to φ1. (See Timing Waveform, Figure 3B.) For applications requiring both indefinite standby and lowest power, standby can be in the φ2 (Sample Unknown) state with two φ1 pulses to generate valid data (see Figure 3C). Valid data now appears two full clock cycles after starting the conversion process. Analog Input Considerations The CA3306 input terminal is characterized by a small capacitance (see Specifications) and a small voltage- dependent current (See Typical Performance Curves). The signal-source impedance should be kept low, however, when operating the CA3306 at high clock rates. CA3306, CA3306A, CA3306C |
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