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FDC37N769 Folha de dados(PDF) 8 Page - SMSC Corporation |
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FDC37N769 Folha de dados(HTML) 8 Page - SMSC Corporation |
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8 / 137 page  SMSC DS – FDC37N769 Page 8 of 137 Rev. 02-16-07 DATASHEET PIN DESCRIPTION BUFFER TYPE PER PIN Table 1 - DESCRIPTION OF PIN FUNCTIONS TQFP PIN # NAME SYMBOL BUFFER TYPE DESCRIPTION HOST PROCESSOR INTERFACE 46-49 51-54 Data Bus 0- 7 D0-D7 IO12 The data bus connection used by the host microprocessor to transmit data to and from the chip. These pins are in a high-impedance state when not in the output mode. 42 nI/O Read nIOR IS This active low signal is issued by the host micropro- cessor to indicate an I/O read operation. 43 nI/O Write nIOW IS This active low signal is issued by the host micropro- cessor to indicate an I/O write operation. 44 Address Enable AEN IS Active high Address Enable indicates DMA operations on the host data bus. Used internally to qualify appropriate address decodes. 26-32 39-41, 95 Address Bus A0-A10 I These host address bits determine the I/O address to be accessed during nIOR and nIOW cycles. These bits are latched internally by the leading edge of nIOR and nIOW. All internal address decodes use the full A0 to A10 address bits. 19,50, 97 DMA Request A, B, C DRQ_A DRQ_B DRQ_C O12 These active high outputs are the DMA request for byte transfers of data between the host and the chip. These signals are cleared on the last byte of the data transfer by the nDACK signal going low (or by nIOR going low if nDACK was already low as in demand mode). 20,34, 94 nDMA Acknowl- edge A, B, C nDACK_A nDACK_B nDACK_C IS These are active low inputs acknowledging the request for a DMA transfer of data between the host and the chip. These inputs enable the DMA read or write internally. 33 Terminal Count TC IS This signal indicates that DMA data transfer is complete. TC is only accepted when nDACK_x is low. In AT and PS/2 model 30 modes, TC is active high and in PS/2 mode, TC is active low. 17, 35-38, 22 Interrupt Request A, C, D, E, F, and H IRQ_A IRQ_C IRQ_D IRQ_E IRQ_F IRQ_H O12/OD12 Interrupt requests from a logical device or IRQIN are output on one of the IRQA-H signals. Refer to the configuration registers section for additional information. If EPP or ECP Mode is enabled this output is pulsed low and released to allow sharing of interrupts. 25 Chip Select Input nCS I This active low input serves as an external decoder for address lines above A10. 55 Reset RESET IS This active high signal resets the chip and must be valid for 500ns minimum. The effect on the internal registers is described in the appropriate section. The configuration registers are not affected by this reset. 98 I/O Channel Ready (Note 4) IOCHRDY OD12 This pin is pulled low to extend the read/write command. IOCHRDY can used by the IRCC and by the Parallel Port in EPP mode. FLOPPY DISK INTERFACE 14 nRead Disk Data nRDATA IS Raw serial bit stream from the disk drive, low active. Each falling edge represents a flux transition of the encoded data. 8 nWrite Gate nWGATE O12/OD12 This active low high current driver allows current to flow through the write head. It becomes active just prior to writing to the diskette. |
Nº de peça semelhante - FDC37N769_07 |
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Descrição semelhante - FDC37N769_07 |
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