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AM29LV160DT-90ED Folha de dados(PDF) 5 Page - Advanced Micro Devices |
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AM29LV160DT-90ED Folha de dados(HTML) 5 Page - Advanced Micro Devices |
5 / 52 page 22358B7 May 5, 2006 Am29LV160D 3 DA TA SH EET TABLE OF CONTENTS Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 5 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 8 Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 9 Table 1. Am29LV160D Device Bus Operations ................................9 Word/Byte Configuration .......................................................... 9 Requirements for Reading Array Data ..................................... 9 Writing Commands/Command Sequences .............................. 9 Program and Erase Operation Status .................................... 10 Standby Mode ........................................................................ 10 Automatic Sleep Mode ........................................................... 10 RESET#: Hardware Reset Pin ............................................... 11 Output Disable Mode .............................................................. 11 Table 2. Sector Address Tables (Am29LV160DT) ..........................12 Table 3. Sector Address Tables (Am29LV160DB) ..........................13 Autoselect Mode ..................................................................... 14 Table 4. Am29LV160D Autoselect Codes (High Voltage Method) ..14 Sector Protection/Unprotection ............................................... 14 Temporary Sector Unprotect .................................................. 15 Figure 1. Temporary Sector Unprotect Operation........................... 15 Figure 2. In-System Sector Protect/Unprotect Algorithms .............. 16 Common Flash Memory Interface (CFI) . . . . . . . 17 Table 5. CFI Query Identification String ..........................................17 Table 6. System Interface String .....................................................18 Table 7. Device Geometry Definition ..............................................18 Table 8. Primary Vendor-Specific Extended Query ........................19 Hardware Data Protection ...................................................... 19 Low VCC Write Inhibit .............................................................. 19 Write Pulse “Glitch” Protection ............................................... 19 Logical Inhibit .......................................................................... 19 Power-Up Write Inhibit ............................................................ 19 Command Definitions . . . . . . . . . . . . . . . . . . . . . . 20 Reading Array Data ................................................................ 20 Reset Command ..................................................................... 20 Autoselect Command Sequence ............................................ 20 Word/Byte Program Command Sequence ............................. 20 Unlock Bypass Command Sequence ..................................... 21 Figure 3. Program Operation .......................................................... 21 Chip Erase Command Sequence ........................................... 21 Sector Erase Command Sequence ........................................ 22 Erase Suspend/Erase Resume Commands ........................... 22 Figure 4. Erase Operation............................................................... 23 Command Definitions ............................................................. 24 Table 9. Am29LV160D Command Definitions ................................24 Write Operation Status . . . . . . . . . . . . . . . . . . . . . 25 DQ7: Data# Polling ................................................................. 25 Figure 5. Data# Polling Algorithm ................................................... 25 RY/BY#: Ready/Busy# ........................................................... 26 DQ6: Toggle Bit I .................................................................... 26 DQ2: Toggle Bit II ................................................................... 26 Reading Toggle Bits DQ6/DQ2 .............................................. 26 Figure 6. Toggle Bit Algorithm......................................................... 27 DQ3: Sector Erase Timer ....................................................... 28 Table 10. Write Operation Status ................................................... 28 Absolute Maximum Ratings . . . . . . . . . . . . . . . . 29 Figure 7. Maximum Negative Overshoot Waveform ...................... 30 Figure 8. Maximum Positive Overshoot Waveform........................ 30 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 30 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) ............................................................. 32 Figure 10. Typical ICC1 vs. Frequency ........................................... 32 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 11. Test Setup..................................................................... 33 Table 11. Test Specifications ......................................................... 33 Figure 12. Input Waveforms and Measurement Levels ................. 33 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 34 Read Operations .................................................................... 34 Figure 13. Read Operations Timings ............................................. 34 Hardware Reset (RESET#) .................................................... 35 Figure 14. RESET# Timings .......................................................... 35 Word/Byte Configuration (BYTE#) ........................................ 36 Figure 15. BYTE# Timings for Read Operations............................ 36 Figure 16. BYTE# Timings for Write Operations............................ 36 Erase/Program Operations ..................................................... 37 Figure 17. Program Operation Timings.......................................... 38 Figure 18. Chip/Sector Erase Operation Timings .......................... 39 Figure 19. Data# Polling Timings (During Embedded Algorithms). 40 Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... 40 Figure 21. DQ2 vs. DQ6 for Erase and Erase Suspend Operations ............................................................ 41 Figure 22. Temporary Sector Unprotect/Timing Diagram .............. 41 Figure 23. Sector Protect/Unprotect Timing Diagram .................... 42 Figure 24. Alternate CE# Controlled Write Operation Timings ...... 44 Erase and Programming Performance . . . . . . . 45 Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 45 TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 45 Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 46 TS 048—48-Pin Standard TSOP ............................................ 46 TSR048—48-Pin Reverse TSOP ........................................... 47 FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 8 x 9 mm ................................................................................ 48 SO 044—44-Pin Small Outline Package ................................ 49 Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 50 Revision A (January 1999) ..................................................... 50 Revision A+1 (April 19, 1999) ................................................. 50 Revision B (November 23, 1999) ............................................ 50 Revision B+1 (February 22, 2000) .......................................... 50 Revision B+2 (November 7, 2000) ......................................... 50 Revision B+3 (November 10, 2000) ....................................... 50 Revision B+4 (April 5, 2004) ................................................... 50 Revision B+5 (June 4, 2004) .................................................. 50 Revision B+6 (October 7, 2004) ............................................. 50 Revision B7 (May 5, 2006) ..................................................... 50 |
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