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L652DU90RF Folha de dados(PDF) 11 Page - Advanced Micro Devices |
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L652DU90RF Folha de dados(HTML) 11 Page - Advanced Micro Devices |
11 / 54 page May 5, 2006 24961A5 Am29LV652D 9 D A TA SH EE T DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the com- mands, along with the address and data information needed to execute the command. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the in- puts and control levels they require, and the resulting output. The following subsections describe each of these operations in further detail. Table 1. Am29LV652D Device Bus Operations Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 11.5–12.5 V, X = Don’t Care, SA = Sector Address, A IN = Address In, DIN = Data In, DOUT = Data Out Notes: 1. CE# can be replaced with CE2# when referring to the second die in the package. CE# and CE2# must not both be driven at the same time. 2. Addresses are A22:A0. Sector addresses are A22:A16. 3. D IN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2). 4. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group Protection and Unprotection” section. 5. All sectors are unprotected when shipped from the factory. VersatileIO ™ (V IO) Control The VersatileIO (V IO) control allows the host system to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data in- puts to the same voltage level that is asserted on V IO. This allows the device to operate in a 3 V or 5 V sys- tem environment as required. For voltage levels below 3 V, contact an AMD representative for more informa- tion. For example, a V I/O of 4.5–5.0 volts allows for I/O at the 5 volt level, driving and receiving signals to and from other 5 V devices on the same data bus. Requirements for Reading Array Data To read array data from the outputs, the system must drive CE# or CE2# and OE# to V IL. CE# or CE2# is the power control and selects the device. OE# is the out- put control and gates array data to the outputs. WE# should remain at V IH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains Operation CE# (Note 1) OE# WE# RESET# ACC Addresses (Note 2) DQ0–DQ7 Read L L H H X AIN DOUT Write (Program/Erase) L H L H X AIN (Note 3) Accelerated Program L H L H V HH AIN (Note 3) Standby VCC ± 0.3 V X X VCC ± 0.3 V H XHigh-Z Output Disable L H H H X XHigh-Z Reset X X X L X XHigh-Z Sector Group Protect (Note 4) L H L V ID X SA, A6 = L, A1 = H, A0 = L (Note 3) Sector Group Unprotect (Note 4) LH L VID X SA, A6 = H, A1 = H, A0 = L (Note 3) Temporary Sector Group Unprotect XX X VID X AIN (Note 3) |
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