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AM41PDS3228DB11IT Folha de dados(PDF) 9 Page - Advanced Micro Devices |
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AM41PDS3228DB11IT Folha de dados(HTML) 9 Page - Advanced Micro Devices |
9 / 59 page 8 Am41PDS3228D May 13, 2002 P R E L IMINARY PIN DESCRIPTION A18–A0 = 19 Address Inputs (Common) A20–A19 = 2 Address Inputs (Flash) SA = Highest Order Address Pin (SRAM) Byte mode DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE1#s = Chip Enable 1 (SRAM) CE2s = Chip Enable 2 (SRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output (Flash) UB#s = Upper Byte Control (SRAM) LB#s = Lower Byte Control (SRAM) CIOs = I/O Configuration (SRAM) CIOs = V IH = Word mode (x16), CIOs = V IL = Byte mode (x8) RESET# = Hardware Reset Pin, Active Low WP#/ACC = Hardware Write Protect/ Acceleration Pin (Flash) V CCf = Flash 1.8 volt-only single power supply (see Product Selector Guide for speed options and voltage sup- ply tolerances) V CCs = SRAM Power Supply V SS = Device Ground (Common) NC = Pin Not Connected Internally LOGIC SYMBOL 19 16 or 8 DQ15–DQ0 A18–A0 CE#f OE# WE# RESET# UB#s RY/BY# WP#/ACC SA A20–A19 LB#s CIOs CE1#s CE2s |
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