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AM49LV128BM Folha de dados(PDF) 3 Page - SPANSION |
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AM49LV128BM Folha de dados(HTML) 3 Page - SPANSION |
3 / 98 page SUPPLEMENT Publication Number: 31022_00 Rev: A Amendment:6 Am49LV128BM Stacked Multi-Chip Package (MCP) 128 Megabit (8 M x 16-Bit) MirrorBit ™ Uniform Sector Flash Memory and 32 Mbit (2 M x 16-Bit) pseudo-static RAM with Page Mode DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES Single power supply operation — 3 volt read, erase, and program operations Manufactured on 0.23 µm MirrorBit process technology SecSi ™ (Secured Silicon) Sector region — 128-word sector for permanent, secure identification through an 8-word random Electronic Serial Number, accessible through a command sequence — May be programmed and locked by the customer Flexible sector architecture — Two hundred fifty-six 32 Kword sectors Compatibility with JEDEC standards — Provides pinout and software compatibility for single- power supply flash, and superior inadvertent write protection Minimum 100,000 erase cycle guarantee per sector 20-year data retention at 125 °C PERFORMANCE CHARACTERISTICS High performance — As fast as 105 ns access time — 25 ns page read times — 0.5 s typical sector erase time — 15 µs typical write buffer word programming time: 16- word write buffer reduces overall programming time for multiple-word updates — 4-word page read buffer — 16-word write buffer Low power consumption (typical values at 3.0 V, 5 MHz) — 30 mA typical active read current — 50 mA typical erase/program current — 1 µA typical standby mode current Package option —64-ball FBGA SOFTWARE & HARDWARE FEATURES Software features — Program Suspend & Resume: read other sectors before programming operation is completed — Erase Suspend & Resume: read/program other sectors before an erase operation is completed — Data# polling & toggle bits provide status — Unlock Bypass Program command reduces overall multiple-word or byte programming time — CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices Hardware features — Sector Group Protection: hardware-level method of preventing write operations within a sector group — Temporary Sector Group Unprotect: VID-level method of changing code in locked sector groups — WP#/ACC input accelerates programming time (when high voltage is applied) for greater throughput during system production. Protects last sector regardless of sector protection settings — Hardware reset input (RESET#) resets device PSRAM FEATURES Asynchronous SRAM Interface Fast Access Time —tCE = tAA = 65 ns max Low Voltage Operating Condition —VDD = 2.7 to + 3.1 V Byte Control by LB# and UB# |
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