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Os motores de busca de Datasheet de Componentes eletrônicos |
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Os motores de busca de Datasheet de Componentes eletrônicos |
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74LVQ241 Folha de dados(PDF) 1 Page - Fairchild Semiconductor |
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74LVQ241 Folha de dados(HTML) 1 Page - Fairchild Semiconductor |
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© 2001 Fairchild Semiconductor Corporation DS011355 www.fairchildsemi.com February 1992 Revised June 2001 74LVQ241 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs General Description The LVQ241 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density. Features s Ideal for low power/low noise 3.3V applications s Implements patented EMI reduction circuitry s Available in SOIC JEDEC, SOIC EIAJ and QSOP pack- ages s Guaranteed simultaneous switching noise level and dynamic threshold performance s Improved latch-up immunity s Guaranteed incident wave switching into 75 Ω s 4 kV minimum ESD immunity Ordering Code: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Diagram IEEE/IEC Pin Descriptions Connection Diagram Truth Tables H = HIGH Voltage Level X = Immaterial L = LOW Voltage Level Z = High Impedance Order Number Package Number Package Description 74LVQ241SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 74LVQ241SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 74LVQ241QSC MQA20 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide Pin Names Description OE1, OE2 3-STATE Output Enable Inputs I0–I7 Inputs O0–O7 Outputs Inputs Outputs OE1 In (Pins 12, 14, 16, 18) L L L L H H H X Z Inputs Outputs OE2 In (Pins 3, 5, 7, 9) L X Z H H H H L L |
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