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FAN5240 Rev. 1.2.0

Pin Configuration

LDRV2

PGND2

BOOT2

HDRV2

SW2

ISNS2

VID4

VID3

VID2

VID1

VID0

FPWM

ILIM

EN

FAN5240

1

2

3

4

5

6

7

8

9

10

11

12

13

14

28

27

26

25

24

23

22

21

20

19

18

17

16

15

VCC

LDRV1

PGND1

BOOT1

HDRV1

SW1

ISNS1

VIN

SS

PGOOD

VCORE+

VCORED

DELAY

AGND

QSOP-28 or TSSOP-28

θ

JA

= 90

°C/W

Pin Assignments

Pin

Number

Pin

Name

Pin Function Description

1

27

LDRV2

LDRV1

Low-Side Drive. The low-side (lower) MOSFET driver output.

2

26

PGND2

PGND1

Power Ground. The return for the low-side MOSFET driver.

3

25

BOOT2

BOOT1

BOOT. The positive supply for the upper MOSFET driver. Connect as shown in Figure 1.

4

24

HDRV2

HDRV1

High-Side Drive. The high-side (upper) MOSFET driver output.

5

23

SW2

SW1

Switching node. The return for the high-side MOSFET driver.

6

22

ISNS2

ISNS1

Current Sense input. Monitors the voltage drop across the lower MOSFET or external

sense resistor for current feedback.

7 –11

VID4–VID0 Voltage Identification Code. Input to VID DAC. Sets the output voltage according to the

codes set as defined in Table Figure . These inputs have 1

µA internal pull-up.

12

FPWM

Forced PWM mode. When logic high, inhibits the chip from entering hysteretic operating

mode. If tied low, hysteretic mode will be allowed.

13

ILIM

Current Limit. A resistor from this pin to GND sets the current limit.

14

EN

EN will also reset the chip after a latched fault condition.

15

AGND

Analog Ground. This is the signal ground reference for the IC. All voltage levels are

measured with respect to this pin.

16

DELAY

Power Good / Over-Current Delay. A capacitor to GND on this pin delays the PGOOD

from going high as well delaying the over-current shutdown.

18

17

VCORE+

VCORE–

VCORE Output Sense. Differential sensing of the output voltage. Used for regulation as

well as PGOOD, under-voltage and over-voltage protection and monitoring. A resistor in

series with this VCORE+ sets the output voltage droop.