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TMP470R1B512PGE Folha de dados(PDF) 7 Page - Analog Devices |
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TMP470R1B512PGE Folha de dados(HTML) 7 Page - Analog Devices |
7 / 49 page www.ti.com TMS470R1B512 16/32-Bit RISC Flash Microcontroller SPNS107A – SEPTEMBER 2005 – REVISED AUGUST 2006 Table 2. Terminal Functions TERMINAL INTERNAL TYPE(1)(2) PULLUP/ DESCRIPTION NAME NO. PULLDOWN(3) HIGH-END TIMER (HET) HET[0] 129 HET[1] 130 HET[2] 137 HET[3] 138 HET[4] 139 HET[5] 140 HET[6] 141 HET[7] 142 HET[8] 79 HET[9] 80 HET[10] 29 HET[11] 28 The B512 device has both the logic and registers for a full 32-I/O HET HET[12] 27 implemented and all 32 pins are available externally. HET[13] 26 Timer input capture or output compare. The HET[31:0] applicable pins can be programmed as general-purpose input/output (GIO) pins. HET[23:0] are HET[14] 25 high-resolution pins and HET[31:24] are standard-resolution pins. HET[15] 24 The high-resolution (HR) SHARE feature allows even HR pins to share the 3.3-V I/O IPD (20 µA) HET[16] 23 next higher odd HR pin structures. This HR sharing is independent of whether or not the odd pin is available externally. If an odd pin is available HET[17] 22 externally and shared, then the odd pin can only be used as a HET[18] 71 general-purpose I/O. For more information on HR SHARE, see the TMS470R1x High-End Timer (HET) Reference Guide (literature number HET[19] 70 SPNU199). HET[20] 69 HET[21] 68 HET[22] 67 HET[23] 123 HET[24] 51 HET[25] 124 HET[26] 125 HET[27] 126 HET[28] 47 HET[29] 48 HET[30] 49 HET[31] 50 HIGH-END CAN CONTROLLER 1 (HECC1) CAN1HTX 88 3.3-V I/O IPU (20 µA) HECC1 transmit pin or GIO pin CAN1HRX 87 3.3-V I/O HECC1 receive pin or GIO pin HIGH-END CAN CONTROLLER 2 (HECC2) CAN2HTX 56 3.3-V I/O IPU (20 µA) HECC2 transmit pin or GIO pin CAN2HRX 57 3.3-V I/O HECC2 receive pin or GIO pin (1) I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect (2) All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high. (3) IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.) 7 Submit Documentation Feedback |
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