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AD7840AQ Folha de dados(PDF) 4 Page - Analog Devices |
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AD7840AQ Folha de dados(HTML) 4 Page - Analog Devices |
4 / 16 page AD7840 REV. B –4– PIN FUNCTION DESCRIPTION DIP Pin Pin No. Mnemonic Function 1 CS /SERIAL Chip Select/Serial Input. When driven with normal logic levels, it is an active low logic input which is used in conjunction with WR to load parallel data to the input latch. For applications where CS is perma- nently low, an R, C is required for correct power-up (see LDAC input). If this input is tied to VSS, it de- fines the AD7840 for serial mode operation. 2 WR/SYNC Write/Frame Synchronization Input. In the parallel data mode, it is used in conjunction with CS to load parallel data. In the serial mode of operation, this pin functions as a Frame Synchronization pulse with se- rial data expected after the falling edge of this signal. 3 D13/SDATA Data Bit 13(MSB)/Serial Data. When parallel data is selected, this pin is the D13 input. In serial mode, SDATA is the serial data input which is used in conjunction with SYNC and SCLK to transfer serial data to the AD7840 input latch. 4 D12/SCLK Data Bit 12/Serial Clock. When parallel data is selected, this pin is the D12 input. In the serial mode, it is the serial clock input. Serial data bits are latched on the falling edge of SCLK when SYNC is low. 5 D11/FORMAT Data Bit 11/Data Format. When parallel data is selected, this pin is the D11 input. In serial mode, a Logic 1 on this input indicates that the MSB is the first valid bit in the serial data stream. A Logic 0 indicates that the LSB is the first valid bit (see Table I). 6 D10/JUSTIFY Data Bit 10/Data Justification. When parallel data is selected, this pin is the D10 input. In serial mode, this input controls the serial data justification (see Table I). 7–11 D9–D5 Data Bit 9 to Data Bit 5. Parallel data inputs. 12 DGND Digital Ground. Ground reference for digital circuitry. 13–16 D4–D1 Data Bit 4 to Data Bit 1. Parallel data inputs. 17 D0 Data Bit 0 (LSB). Parallel data input. 18 VDD Positive Supply, +5 V ± 5%. 19 AGND Analog Ground. Ground reference for DAC, reference and output buffer amplifier. 20 VOUT Analog Output Voltage. This is the buffer amplifier output voltage. Bipolar output range ( ±3 V with REF IN = +3 V). 21 VSS Negative Supply Voltage, –5 V ± 5%. 22 REF OUT Voltage Reference Output. The internal 3 V analog reference is provided at this pin. To operate the AD7840 with internal reference, REF OUT should be connected to REF IN. The external load capability of the reference is 500 µA. 23 REF IN Voltage Reference Input. The reference voltage for the DAC is applied to this pin. It is internally buffered before being applied to the DAC. The nominal reference voltage for correct operation of the AD7840 is 3 V. 24 LDAC Load DAC. Logic Input. A new word is loaded into the DAC latch from the input latch on the falling edge of this signal (see Interface Logic Information section). The AD7840 should be powered-up with LDAC high. For applications where LDAC is permanently low, an R, C is required for correct power-up (see Figure 19). Table I. Serial Data Modes |
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