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SA1620 Folha de dados(PDF) 4 Page - NXP Semiconductors |
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SA1620 Folha de dados(HTML) 4 Page - NXP Semiconductors |
4 / 26 page Philips Semiconductors Product specification SA1620 Low voltage GSM front-end transceiver 1997 May 22 4 PIN DESCRIPTIONS Pin No. Pin Name Description DC Regulators 15 GND1 Ground of regulator supply 18 GND2 Ground of regulator supply 21 GND3 Ground of regulator supply 26 CON2 Control 2, voltage select for regulator 1 and 2 29 CON1 Control 1, voltage select for regulator 1 and 2 30 GNDREG2 Ground of regulator 2 31 VREG2 Output of regulator 2 32 VREG2F2 Feedback of regulator 2 33 VREG1 Output of regulator 1 34 GNDREG1 Ground of regulator 1 35 PON Power-on input of regulators 36 VBATT Input of regulator 1 and 2 Rx Path 1 VCCL2 Positive supply for LNA2 2 IN2 Input LNA2 3 GNDL2 Ground L2 for LNA2 4 GNDL2A Ground L2A for LNA2 5 OUT2 Output LNA2 6 B Attenuation select B for LNA1 and LNA2 7 A Attenuation select A for LNA1 and LNA2 8 INM RF input for Rx mixer, open emitter 9 INMX Inverse RF input for Rx mixer, open emitter 10 COMP2 Capacitor for bias stabilization 11 COMP1 Capacitor for bias stabilization 12 VCCBM VCC for Rx Bias and Rx mixer Pin No. Pin Name Description 13 GNDBM Ground for Rx Bias and Rx mixer 14 PONRx Power on input for Rx bias supply 16 RxIF IF output, open collector 17 RxIFX Inverse IF output, open collector 44 IN1 Input to LNA1 45 GNDL1 Ground L1 for LNA1 46 GNDL1A Ground L1A for LNA1 47 OUT1 Output LNA1 48 VCCL1 Positive supply for LNA1 Tx Path 19 TxIF IF input for Tx 20 TxIFX Inverse IF input for Tx 22 VCCTx1 Positive supply for Tx input 23 GNDTx1 Ground for Tx input 24 VCCTx2 Positive supply for LO and Tx input 25 GNDTx2 Ground for LO and Tx input 38 PDTx Power down Tx input 39 GNDTx4 Ground for Tx output 40 TxOX Inverse Tx output, open collector 41 TxO Tx output, open collector 42 GNDTx3 Ground 1 for Tx output side 43 RETx Reference resistor for Tx output current Elements for Tx and Rx Path 27 LO IN Input for Local Oscillator signal 28 LO INX Inverse input for LO or AC ground 37 PONBUF Power on first stage LO input buffer and bias NOTES: 1. Device is ESD sensitive. There are no ESD protection diodes at Pins 16, 17, 40 and 41. Thus, open-collector outputs may have increased DC voltage or higher AC peak voltage. 2. Pins 15, 18 and 21 are connected to each other and to a separate ground in REG1 and REG2. 3. Pins 23, 25, 42 and 39 are connected to each other and to the Tx path, LO buffer and associated bias supplies. 4. Pins 22 and 24 are connected to each other providing a sense input. They are also connected to the Tx path, LO buffer and associated bias supplies. 5. Pins 30 and 34 are not internally connected. They must be connected to external grounds. 6. Pins 48, 1, and 12 are not internally connected and have no ESD protection diodes between them. Power may be saved by connecting VCCL1 and IN1 or VCCL2 and IN2 to ground if LNA1 or LNA2 is not needed. |
Nº de peça semelhante - SA1620 |
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Descrição semelhante - SA1620 |
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