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SA2420DH Folha de dados(PDF) 2 Page - NXP Semiconductors

Nome de Peças SA2420DH
Descrição Electrónicos  Low voltage RF transceiver . 2.45GHz
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Fabricante Electrônico  PHILIPS [NXP Semiconductors]
Página de início  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

SA2420DH Folha de dados(HTML) 2 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
SA2420
Low voltage RF transceiver — 2.45 GHz
2
1997 May 23
853–1984 18069
DESCRIPTION
The SA2420 transceiver is a combined low-noise amplifier, receive
mixer, transmit mixer and LO buffer IC designed for
high-performance low-power communication systems for
2.4-2.5GHz applications. The LNA has a 2.5dB noise figure at
2.45GHz with 14dB gain and an IP3 intercept of -3dBm at the input.
The gain is stabilized by on-chip compensation to vary less than
±0.2dB over the -40 to +85°C temperature range. The
wide-dynamic-range receive mixer has a 10.9dB noise figure and an
input IP3 of +2.8dBm at 2.45GHz. The nominal current drawn from
a single 3V supply is 37mA in transmit mode and 22mA in receive
mode.
FEATURES
Low current consumption: 37mA nominal transmit mode and
22mA nominal receive mode
Fabricated on a high volume, rugged BiCMOS technology
High system power gain: 22.5dB (LNA + Mixer) at 2.45GHz
TSSOP24 package
Excellent gain stability versus temperature and supply voltage
-10dBm LO input power can be used to drive the mixer
Operates with either full or half frequency LO
Wide IF range: 50–500MHz
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
24
23
22
21
20
19
18
17
16
15
DH Package
ATTEN SW
Tx/Rx SW
GND
RF IN/OUT
GND
GND
GND
LNA OUT
VCC
GND
GND
Rx IF OUT
GND
LOP
LNA IN
GND
GND
Rx IF OUT
Tx IF IN
Tx IF IN
LO SW
LOM
VCC LO
CHIP EN
SR00164
Figure 1.
Pin Configuration
APPLICATIONS
2.45GHz WLAN front-end (802.11, ISM)
ORDERING INFORMATION
DESCRIPTION
TEMPERATURE RANGE
ORDER CODE
DWG #
24-Pin Plastic Thin Shrink Small Outline Package (Surface-mount, TSSOP)
-40 to +85
°C
SA2420DH
SOT355-1
BLOCK DIAGRAM
4
3
2
15
24
23
22
21
20
7
610
9
8
19
18
17
16
15
LO
GND
LOP
GND
VCC
RF IN/
OUT
GND
ATTEN
SW
CHIP
EN
GND
GND
LNA
OUT
SW
GND
LNA
GND
GND
12
11
14
13
LOM
LO
Tx/Rx
SW
GND
VCC
LNA
IN
Rx IF
OUT
Rx IF
OUT
Tx IF
IN
Tx IF
IN
RX
RX
TX
BUFFER
FREQ.
DBLER
BPF
BPF
PRE-DRIVER
TX
ATTENUATOR
SR00165
X2
X1
Figure 2.
SA2420 Block Diagram


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