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TDA1311A Folha de dados(PDF) 5 Page - NXP Semiconductors |
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TDA1311A Folha de dados(HTML) 5 Page - NXP Semiconductors |
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5 / 20 page  1995 Dec 18 5 Philips Semiconductors Preliminary specification Stereo Continuous Calibration DAC (CC-DAC) TDA1311A FUNCTIONAL DESCRIPTION The basic operation of the continuous calibration DAC is illustrated in Fig.3. The figure shows the calibration and operation cycle. During calibration of the MOS current source (see Fig.3a) transistor M1 is connected as a diode by applying a reference current. The voltage Vgs on the intrinsic gate-source capacitance Cgs of M1 is then determined by the transistor characteristics. After calibration of the drain current to the reference value IREF, the switch S1 is opened and S2 is switched to the other position (see Fig.3b). The gate-to-source voltage Vgs of M1 is not changed because the charge on Cgs is preserved. Therefore, the drain current of M1 will still be equal to IREF and this exact duplicate of IREF is now available at the OUT terminal. The 32 current sources and the spare current source of the TDA1311A; AT are continuously calibrated (see Fig.1). The spare current source is included to allow continuous converter operation. The output of one calibrated source is connected to an 11-bit binary current divider consisting of 2048 transistors. A symmetrical offset decoding principle is incorporated that arranges the bit switching in such a way that the zero-crossing is performed only by switching the LSB currents. The TDA1311A; AT (CC-DAC) accepts serial input data formats of 16-bit word length. Left and right data words are time multiplexed. The most significant bit (bit 1) must always be first. The input data format is shown in Figs 4 and 5. With a HIGH level on the word select input (WS), data is placed in the left input register and with a LOW level on the WS input, data is placed in the right input register (see Fig.1). The data in the input registers are simultaneously latched in the output registers which control the bit switches. An internal offset voltage VOS is added to the full scale output voltage VFS; VOS and VFS are proportional to VDD: VDD1/VDD2 =VFS1/VFS2 =VOS1/VOS2. Fig.3 Calibration principle. handbook, full pagewidth MBG860 out S2 S1 M1 Cgs Vgs Cgs Vgs out S2 S1 M1 Iref Iref Iref (a) (b) (a) = calibration. (b) = operation. |
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