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TDA4882 Folha de dados(PDF) 6 Page - NXP Semiconductors |
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TDA4882 Folha de dados(HTML) 6 Page - NXP Semiconductors |
6 / 28 page 1997 Sep 04 6 Philips Semiconductors Product specification Advanced monitor video controller for OSD TDA4882 7.5 Input clamping The clamping pulse (Fig.17) is for input clamping only. The input signals are at black level during the clamping pulse and are clamped to an internal artificial black level. The coupling capacitors provide black-level storage. The threshold for the clamping pulse is higher than that for vertical blanking, therefore, the rise and fall times of the clamping pulse need to be faster than 75 ns/V during transition from 1 to 3.5 V. 7.6 Vertical blanking The vertical blanking pulse (Fig.17) will be detected if the input voltage is higher than the threshold voltage for approximately 320 ns but does not exceed the threshold for the clamping pulse in the time between. During the vertical blanking pulse the input clamping is disabled to avoid misclamping in the event of composite input signals. The input signal is blanked and the artificial black level is inserted instead. Also the brightness is set internally to its nominal value, thus the output signal is at reference black level. The DC value of the reference black level will be adjusted by cut-off stabilization. 7.7 Horizontal blanking During horizontal blanking (Fig.18) the output signal is set to reference black level and output clamping is activated. If the voltage exceeds the switch-off threshold, the signal is blanked and switched to ultra-black level for screen protection and spot suppression during V-flyback. Ultra-black level is the lowest possible channel output voltage and is not dependent on cut-off stabilization. 7.8 Cut-off and black-level stabilization For cut-off stabilization (DC coupling to the CRT) and black-level stabilization (AC coupling) the video signal at the cathode or the coupling capacitor is divided by an adjustable voltage divider and fed to the channel feedback inputs. During horizontal blanking time this signal is compared with an internal DC voltage of approximately 5.8 V. Any difference will lead to a reference black-level correction by charging or discharging the integrated capacitor which stores the reference black-level information between the horizontal blanking pulses. 7.9 On Screen Display For OSD (Fig.3), fast switching of control pin 6 to less than 1 V (e.g. 0.7 V) blanks the input signals. The OSD signals can easily be inserted to the external cascode transistor. 7.10 Test mode During test mode (pins 9 and 10 connected to VP) the black levels at the channel voltage outputs are set internally to typical 0.7 V with nominal brightness and 3 V DC at channel signal inputs. Fig.3 OSD application. handbook, full pagewidth MHA816 OSD fast blanking 4.7 k Ω 1 k Ω 150 Ω 220 Ω 100 pF 20 channel 1 channel 2 current output BFQ235 PH2222 channel 3 OSD signal input TDA4882 contrast 17 14 6 depending on channel gain 1 k Ω to 10 kΩ PH2222 |
Nº de peça semelhante - TDA4882 |
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Descrição semelhante - TDA4882 |
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