1998 Sep 03

6

Philips Semiconductors

Preliminary specification

Full bridge current driven vertical deflection

output circuit in LVDMOS

TDA8354Q

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

Notes

1. When the pin voltage exceeds 70 V the device behaves like a power zener diode thus limiting the voltage.

2. Internally limited by thermal protection; switching point

≈170 °C.

5. Machine model: equivalent to discharge a 200 pF capacitor through a 0

Ω series resistor. Except pin 7: ±250 V.

6. Human body model: equivalent to discharge a 100 pF capacitor through a 1.5 k

Ω series resistor. Except pin 7:

±1500 V.

SYMBOL

PARAMETER

CONDITIONS

MIN.

MAX.

UNIT

DC supply

supply voltage

−

18

V

flyback supply voltage

−

68

V

Vertical circuit

output current (peak-to-peak value)

−

3.2

A

output voltage (pin 9)

note 1

−

68

V

output voltage (pin 5)

−

V

current into or out of

pins 1 to 3 and 11 to 13

−20

+20

mA

peak voltage on pins 1 to 3 and 11 to 13

−0.5

V

Flyback switch

peak output current

−±1.6

A

Thermal data (in accordance with IEC 747-1)

storage temperature

−55

+150

°C

operating ambient temperature

−25

+75

°C

junction temperature

note 2

−

150

°C

Miscellaneous

short-circuiting time

note 3

−

1h

current into any pin

+1.5

−

+200

mA

current out of any pin

−200

−

mA

electrostatic handling

note 5

−±300

V

note 6

−±2000

V