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DAC-08 Folha de dados(PDF) 10 Page - ON Semiconductor |
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DAC-08 Folha de dados(HTML) 10 Page - ON Semiconductor |
10 / 14 page DAC−08 SERIES http://onsemi.com 10 Settling Time The worst-case switching condition occurs when all bits are switched on, which corresponds to a low-to-high transition for all input bits. This time is typically 70 ns for settling to within LSB for 8-bit accuracy. This time applies when RL < 500 W and CO < 25 pF. The slowest single switch is the least significant bit, which typically turns on and settles in 65 ns. In applications where the DAC functions in a positive-going ramp mode, the worst-case condition does not occur and settling times less than 70 ns may be realized. Extra care must be taken in board layout since this usually is the dominant factor in satisfactory test results when measuring settling time. Short leads, 100 mF supply bypassing for low frequencies, minimum scope lead length, and avoidance of ground loops are all mandatory. NOTES: D1, D2 = IN6263 or equivalent D3 = IN914 or equivalent C1 = 0.01mF C2, C3 = 0.1mF Q1 = 2N3904 C4, C5 = 15pF and includes all probe and fixturing capacitance. VIN VS + = +15V VADJ VOUT VS − = −15V R15 = 5kW IREF = 2mA VREF = 10V R14 = 5kW VOUT R1 = 1000W R2 = 1000W R3 = 500W 50 W C1 C2 C5 C3 D3 D1 D2 C4 DUT 14 15 16 3 1 2 4 12 11 10 9 8 7 6 5 Q1 Figure 24. Settling Time and Propagation Delay NOTES: I FS [ ) V REF R REF x 255 256 ;I O ) I O + I FS for all logic states MSB 2 34567 LSB 5 6789 10 11 12 14 15 316 13 1 2 4 DAC-08 (LOW T.C.) V+ V− IO IO +VREF IREF RREF CCOMP 0.1 mF 0.1 mF Figure 25. Basic DAC−08 Configuration |
Nº de peça semelhante - DAC-08 |
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Descrição semelhante - DAC-08 |
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